F. Iga

A 600MHz MTJ-based nonvolatile latch making use of incubation time in MTJ switching

The incubation (transit) time of the perpendicular magnetic tunnel junction (MTJ) is found shorter (longer) than the in-plane MTJ. By making use of the incubation time, a new concept is proposed for MTJ/CMOS hybrid circuits that operate as fast as CMOS circuits without operation power overhead and with negligible MTJ switching error. A nonvolatile latch based on the concept is fabricated in 90nm technology to demonstrate 600MHz stable operation.

Novel 2step Writing Method for STT-RAM to Improve Switching Probability and Write Speed

to Improve Switching Probability and Write Speed Fumitaka Iga, Yasuhiko Suzuki, Takashi Ohsawa, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, and Tetsuo Endoh 1 Center for Interdisciplinary Research, Tohoku University, Aramaki Aza-Aoba 6-3, Aoba-ku, Sendai 980-8578, Japan Phone: +81-22-795-4401 E-mail: endoh@riec.tohoku.ac.jp 2 Center for Spintronics Integrated Systems, Tohoku University, 2-1-1 Katahira, Aoba-ku, Sendai 980-8577, Japan 3 Research Institute of Electrical Communication, Tohoku University, 2-1-1 Katahira, Aoba-ku, Sendai 980-8577, Japan

The Performance of Magnetic Tunnel Junction Integrated on the Back-End Metal Line of Complimentary Metal?Oxide?Semiconductor Circuits

In this paper, we have described the complementary metal–oxide–semiconductor (CMOS)/magnetic tunnel junction (MTJ) integrated process technology; MTJs were fabricated on via metal with surface roughness of 0.3 nm with 0.14 µm CMOS process and 60 ×180 nm2 MTJ process. It is shown that by this process technology, the fabricated MTJ on CMOS logic circuit plane achieves a large change in a resistance of 3.63 kΩ (anti-parallel) with the TMR ratio of 138% at room temperature, which is large enough for a sensing scheme of standard CMOS logic. Furthermore, we have successfully demonstrated the DC and AC operation of this MTJ with write transistors. As the results, our MTJ achieves high enough write/read performance with transistors for realizing MTJ-based logic circuits.

The Performance of Magnetic Tunnel Junction Integrated on the Back-end Metal Line of CMOS Circuits

Center for Interdisciplinary Research, Tohoku University, Aramaki aza Aoba 6-3, Aoba-ku, Sendai 980-8578, Japan, Phone: +81-22-217-4401 E-mail: endoh@riec.tohoku.ac.jp 2 Laboratory for Nanoelectronics and Spintronics, Research Institute of Electrical Communication, Tohoku University, 2-1-1 Katahira, Aoba-ku, Sendai 980-8577, Japan Advanced Research Laboratory, Hitachi, Ltd., Kokubunji, Tokyo 185-8601, Japan 4 Research Institute of Electrical Communication, Tohoku University, 2-1-1 Katahira, Aoba-ku, Sendai 980-8577, Japan