Tetsuo Endoh

Fabrication of a Nonvolatile Full Adder Based on Logic-in-Memory Architecture Using Magnetic Tunnel Junctions

Nonvolatile logic-in-memory architecture, where nonvolatile memory elements are distributed over a logic-circuit plane, is expected to realize both ultra-low-power and reduced interconnection delay. We have fabricated a nonvolatile full adder based on logic-in-memory architecture using magnetic tunnel junctions (MTJs) in combination with metal oxide semiconductor (MOS) transistors. Magnesium oxide (MgO) barrier MTJs are used to take advantage of their high tunnel magneto-resistance (TMR) ratio and spin-injection write capability. The MOS transistors are fabricated using a 0.18 µm complementary metal oxide semiconductor (CMOS) process. The basic operation of the full adder is confirmed.

Reliability issues of flash memory cells

Reliability issues for flash electrically erasable programmable read-only memories are reviewed. The reliability of both the source-erase type (ETOX) flash memory and the NAND structure EEPROM are discussed. Disturbs during programming, write/erase endurance, charge loss of both devices are reviewed, and the reliability of the tunnel oxide and the interpoly dielectric are described. It is shown that bipolarity F-N programming/erase, which is used in the NAND EEPROM, improves the charge to breakdown and decreases the stress-induced leakage current. >

0.18-/spl mu/m CMOS 10-Gb/s multiplexer/demultiplexer ICs using current mode logic with tolerance to threshold voltage fluctuation

A feedback MOS current mode logic (MCML) is proposed for the high-speed operation of CMOS transistors. This logic is more tolerant to the threshold voltage fluctuation than the conventional MCML and is suitable for gigahertz operation of deep-submicron CMOS transistors. Using this logic, 8:1 multiplexer (MUX) and 1:8 demultiplexer (DEMUX) ICs for optical-fiber-link systems have been fabricated with 0.18-/spl mu/m CMOS transistors. The ICs are faster than conventional CMOS MUX and DEMUX ICs and their power consumption is less than 1/4 of that of the conventional 10-Gb/s MUX and DEMUX ICs made using Si bipolar or GaAs transistors.

Novel ultra high density flash memory with a stacked-surrounding gate transistor (S-SGT) structured cell

In order to overcome the limitation of cell area of 4F/sup 2/ per bit in conventional NAND flash memory cells, stacked-surrounding gate transistor (S-SGT) structured cell is proposed. The new structured cell achieves cell area of 4F/sup 2//N per bit, where N is the number of stacked memory cells in one silicon pillar, without using multibit per memory cell technology. The S-SGT structured cell consisting of 2 stacked memory cells in one silicon pillar achieves cell area per bit less than 50% of the smallest reported NAND structured cell. The novel S-SGT structured cells are fabricated by vertical self-aligned processes using a 0.2/spl mu/m design rule. The S-SGT, structured cell can be programmed and erased by uniform injection and uniform emission of Fowler-Nordheim (F-N) tunneling electrons over the whole channel area of the memory cell, respectively, the same as conventional NAND structured cell. This high performance S-SGT structured cell is applicable to high-density nonvolatile memories as large as 16G/64G bit flash memory or beyond.

Fast and accurate programming method for multi-level NAND EEPROMs

For the replacement of conventional hard disks by NAND EEPROMs, a very high density and a high programming speed are required. An increased density can be achieved by using multi-level memory cells. With the new method, using staircase programming pulses combined with a bit-by-bit verify, a very narrow threshold voltage distribution of 0.7 V, necessary for 4-level or 2-bit operation, and a high programming speed of 300 /spl mu/s/page or 590 ns/byte can be obtained.

A NAND structured cell with a new programming technology for highly reliable 5 V-only flash EEPROM

A programming technology is proposed to improve the endurance and read retention characteristics of NAND-structured EEPROM cells programmed by Fowler-Nordheim tunneling of electrons. Erasing and writing are accomplished uniformly over the whole channel area instead of nonuniform erasing at the drain. To achieve programming over the whole channel area, a new device structure is also proposed. The high-voltage pulses can be easily generated on a chip from a single 5-V power supply because the direct current due to the avalanche breakdown does not flow. The gate length of the memory transistor is 1.0 μm. Using 1.0 μm rules, the cell size per bit is 11.7 μm2

Standby-Power-Free Compact Ternary Content-Addressable Memory Cell Chip Using Magnetic Tunnel Junction Devices

A compact ternary content-addressable memory (TCAM) cell of 3.15 µm2 with a 0.14 µm complementary metal oxide semiconductor process is realized by the use of nonvolatile magnetic tunnel junction (MTJ) devices with spin-injection write. This TCAM cell based on logic-in-memory architecture with nonvolatile MTJs needs no standby power, yet allows instant shut-down of the supply voltage without data backup to an external nonvolatile device.

A reliable bi-polarity write/erase technology in flash EEPROMs

The authors describe a technology for scaling down the flash EEPROM cell, which has a conventional self-aligned double poly-Si stacked structure. It is clarified experimentally that a flash memory cell written and erased by Fowler-Nordheim (F-N) tunneling has ten times the retention time of the conventional cell, which is written by channel-hot-electron (CHE) injection and erased by F-N tunneling. This difference of data retentivity between these two write/erase (W/E) technologies is due to decreasing the thin gate oxide leakage current by bi-polarity F-N tunneling stress. This improvement in data retention becomes more pronounced as the gate oxide thickness decreases. Therefore, a bipolarity F-N tunneling WE technology, which enables a flash EEPROM cell to scale down its oxide thickness, shows promise as a key technology for realizing 16 Mb flash EEPROMs and beyond.<<ETX>>

Magnetic tunnel junction for nonvolatile CMOS logic

Magnetic tunnel junction (MTJ) device, a nonvolatile spintronic device, is capable of fast-read/write with high endurance together with back-end-of-the-line (BEOL) compatibility, offering a possibility of constructing not only stand-alone RAMs and embedded RAMs that can be used in conventional VLSI circuits and systems but also low-power high-performance nonvolatile CMOS logic employing logic-in-memory architecture. The advantages of employing MTJs with CMOS circuits are discussed and the current status of the MTJ technology is presented along with its prospect and remaining challenges.

An accurate model of subbreakdown due to band-to-band tunneling and some applications

The authors describe a novel accurate model and numerical analysis of subbreakdown phenomena due to band-to-band tunneling in a thin-gate-oxide n-MOSFET. Subbreakdown I-V characteristics are calculated for various oxide thicknesses. The results agree with experimental results over a wide range of subbreakdown current from 10/sup -12/ A to 10/sup -6/ A. The numerical analysis based on this model has been utilized to suppress the subbreakdown current. It is concluded that the model can be utilized for the design of thin-gate-oxide devices. >