Shoji Ikeda

Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-Vector Prediction

A magnetic tunnel junction (MTJ)-based logic-in-memory hardware accelerator LSI with cycle-based power gating is fabricated using a 90 nm MTJ/MOS process on a 300 mm wafer fabrication line for practical-scale, fully parallel motion-vector prediction, without wasted power dissipation. The proposed nonvolatile LSI is designed by establishing an automated design environment with MTJ-based logic-circuit IPs and peripheral assistant tools, as well as a precise MTJ device model produced by the fabricated test chips. Through the measurement results of the fabricated LSI, this study shows both the impact of the power-gating technique in a fine temporal granularity utilizing the non-volatility of the MTJ device and the effectiveness of the established automated design environment for designing random logic LSI using nonvolatile logic-in-memory.

Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure

A nonvolatile FPGA (NVFPGA) test chip, where 3000 6-input lookup table (LUT) circuits are embedded, is fabricated under 90nm CMOS/75nm perpendicular magnetic tunnel junction (p-MTJ) technologies. The use of a p-MTJ device makes data-backup-limitation free, which essentially eliminates damage control to nonvolatile storage devices. The use of a p-MTJ device also enables the extension towards dynamically reconfigurable logic paradigm. Since hardware components are shared among all the p-MTJ devices by the use of logic-in-memory structure, the effective area of the 6-input LUT circuit is reduced by 56% compared to that of an SRAM-based one. Moreover, block-level power gating, in which all the idle function blocks are optimally turned off in accordance with the operation mode, can minimize static power consumption of each tile. As a result, the total average power of the proposed NVFPGA is reduced by 81% in comparison with that of an SRAM-based FPGA under typical benchmark-circuit realizations.

Power-gated 32 bit microprocessor with a power controller circuit activated by deep-sleep-mode instruction achieving ultra-low power operation

A spintronic-based power-gated micro-processing unit (MPU) is proposed. It includes a power control circuit activated by the newly supported power-off instruction for the deep-sleep mode. These means enable the power-off procedure for the MPU to be executed appropriately. A test chip was designed and fabricated using 90 nm CMOS and an additional 100 nm MTJ process; it was successfully operated. The guideline of the energy reduction effects for this MPU was presented, using the estimation based on the measurement results of the test chip. The result shows that a large operation energy reduction of 1/28 can be achieved when the operation duty is 10%, under the condition of a sufficient number of idle clock cycles.

Improvement of Thermal Tolerance of CoFeB–MgO Perpendicular-Anisotropy Magnetic Tunnel Junctions by Controlling Boron Composition

We investigated annealing temperature Ta dependence of tunnel magnetoresistance (TMR) ratio and magnetic properties for perpendicular-anisotropy (CoFe)100-XBX/MgO magnetic tunnel junctions (MTJs) with single (CoFe)100-XBX/MgO interface (s-MTJ) and double CoFeB-MgO interface (d-MTJ) structures with various boron compositions X. High TMR ratio over 100% was observed in the s-MTJ with X= 35 at.% after annealing at 360°C-400°C, whereas the s-MTJ with X = 30 at.% showed the degradation of TMR ratio with the increase of Ta above 360°C, resulting from the decrease of perpendicular anisotropy. The d-MTJ with X = 25 at.% maintained high TMR ratio up to Ta = 400°C owing to its higher perpendicular anisotropy compared with the s-MTJ. The difference of perpendicular anisotropy between the s-MTJ and the d-MTJ can be attributed to higher interfacial anisotropy together with lower saturation magnetization of the d-MTJs. The lower saturation magnetization is attributable to two MgO layers that suppress boron diffusion from CoFeB layers, which was verified by cross-sectional line analysis using electron energy-loss spectroscopy.

1T1MTJ STT-MRAM Cell Array Design with an Adaptive Reference Voltage Generator for Improving Device Variation Tolerance

A device-variation-tolerant spin-transfer-torque magnetic random access memory (STT-MRAM) cell array design with a high-signal-margin reference generator circuit was developed to create high-density 1T1MTJ STT-MRAMs. To realize an appropriate STT-MRAM design, fluctuations in the memory cell characteristics were first measured using a 1-kbit STT-MRAM test chip. Based on these measurements, a reference generator and an STT-MRAM cell array architecture were proposed. This cell array was evaluated in terms of the signal margin for read operation and its tolerance to device variation by means of Monte-Carlo SPICE circuit simulations. The proposed design enables a 50% improvement in the signal margin compared with the conventional cell array circuit.

Evidence of a reduction reaction of oxidized iron/cobalt by boron atoms diffused toward naturally oxidized surface of CoFeB layer during annealing

We have investigated the redox reaction on the surface of Ta/CoFeB/MgO/CoFeB magnetic tunnel junction stack samples after annealing at 300, 350, and 400u2009°C for 1u2009h using angle-resolved X-ray photoelectron spectroscopy for precise analysis of the chemical bonding states. At a capping tantalum layer thickness of 1u2009nm, both the capping tantalum layer and the surface of the underneath CoFeB layer in the as-deposited stack sample were naturally oxidized. By comparison of the Co 2p and Fe 2p spectra among the as-deposited and annealed samples, reduction of the naturally oxidized cobalt and iron atoms occurred on the surface of the CoFeB layer. The reduction reaction was more significant at higher annealing temperature. Oxidized cobalt and iron were reduced by boron atoms that diffused toward the surface of the top CoFeB layer. A single CoFeB layer was prepared on SiO2, and a confirmatory evidence of the redox reaction with boron diffusion was obtained by angle-resolved X-ray photoelectron spectroscopy analysis of the naturally oxidized surface of the CoFeB single layer after annealing. The redox reaction is theoretically reasonable based on the Ellingham diagram.

Study on initial current leakage spots in CoFeB-capped MgO tunnel barrier by conductive atomic force microscopy

Although a microscopic study on a MgO tunnel barrier by atomic force microscopy has been required to study the reliability of magnetic tunnel junctions, the deterioration of bare MgO due to the adsorption of H2O and CO2 has been a problem. For an accurate evaluation of the initial current leakage spots distributed in a MgO tunnel barrier, a CoFeB-capped MgO tunnel barrier structure is proposed for evaluation by means of conductive atomic force microscopy. The CoFeB capping layer thickness was optimized to be 2.0 nm to prevent H2O and CO2 adsorption on the MgO and to minimize the series resistance due to the capping layer. The initial current leakage spot density of the MgO tunnel barrier with the optimized CoFeB capping layer exponentially increased as the thickness of the MgO tunnel barrier decreased from 1.6 to 0.8 nm, and was 157 spots/µm2 at the MgO thickness of 1.2 nm and the bias voltage of 0.5 V.

A spin transfer torque magnetoresistance random access memory-based high-density and ultralow-power associative memory for fully data-adaptive nearest neighbor search with current-mode similarity evaluation and time-domain minimum searching

A high-density nonvolatile associative memory (NV-AM) based on spin transfer torque magnetoresistive random access memory (STT-MRAM), which achieves highly concurrent and ultralow-power nearest neighbor search with full adaptivity of the template data format, has been proposed and fabricated using the 90 nm CMOS/70 nm perpendicular-magnetic-tunnel-junction hybrid process. A truly compact current-mode circuitry is developed to realize flexibly controllable and high-parallel similarity evaluation, which makes the NV-AM adaptable to any dimensionality and component-bit of template data. A compact dual-stage time-domain minimum searching circuit is also developed, which can freely extend the system for more template data by connecting multiple NM-AM cores without additional circuits for integrated processing. Both the embedded STT-MRAM module and the computing circuit modules in this NV-AM chip are synchronously power-gated to completely eliminate standby power and maximally reduce operation power by only activating the currently accessed circuit blocks. The operations of a prototype chip at 40 MHz are demonstrated by measurement. The average operation power is only 130 µW, and the circuit density is less than 11 µm2/bit. Compared with the latest conventional works in both volatile and nonvolatile approaches, more than 31.3% circuit area reductions and 99.2% power improvements are achieved, respectively. Further power performance analyses are discussed, which verify the special superiority of the proposed NV-AM in low-power and large-memory-based VLSIs.

A 600-µW ultra-low-power associative processor for image pattern recognition employing magnetic tunnel junction-based nonvolatile memories with autonomic intelligent power-gating scheme

A novel associative processor using magnetic tunnel junction (MTJ)-based nonvolatile memories has been proposed and fabricated under a 90 nm CMOS/70 nm perpendicular-MTJ (p-MTJ) hybrid process for achieving the exceptionally low-power performance of image pattern recognition. A four-transistor 2-MTJ (4T-2MTJ) spin transfer torque magnetoresistive random access memory was adopted to completely eliminate the standby power. A self-directed intelligent power-gating (IPG) scheme specialized for this associative processor is employed to optimize the operation power by only autonomously activating currently accessed memory cells. The operations of a prototype chip at 20 MHz are demonstrated by measurement. The proposed processor can successfully carry out single texture pattern matching within 6.5 µs using 128-dimension bag-of-feature patterns, and the measured average operation power of the entire processor core is only 600 µW. Compared with the twin chip designed with 6T static random access memory, 91.2% power reductions are achieved. More than 88.0% power reductions are obtained compared with the latest associative memories. The further power performance analysis is discussed in detail, which verifies the special superiority of the proposed processor in power consumption for large-capacity memory-based VLSI systems.

Diffusion behaviors observed on the surface of CoFeB film after the natural oxidation and the annealing

This experiment investigates the reduction reaction of oxidized Fe/Co by B on the naturally oxidized surface of the CoFeB film after annealing. The focus is on the diffusion behaviors of the constituent elements at the film surface after natural oxidation and annealing to elucidate the oxidation and reduction mechanisms of the film. Surface sputtering and X-ray photoelectron spectroscopy are performed for depth profile analysis. The diffusion behaviors during the natural oxidation of the CoFeB film is speculated to be related to the amount of the standard free energy of the formation of oxides.