Takahiro Hanyu

Magnetic tunnel junction for nonvolatile CMOS logic

Magnetic tunnel junction (MTJ) device, a nonvolatile spintronic device, is capable of fast-read/write with high endurance together with back-end-of-the-line (BEOL) compatibility, offering a possibility of constructing not only stand-alone RAMs and embedded RAMs that can be used in conventional VLSI circuits and systems but also low-power high-performance nonvolatile CMOS logic employing logic-in-memory architecture. The advantages of employing MTJs with CMOS circuits are discussed and the current status of the MTJ technology is presented along with its prospect and remaining challenges.

10.5 A 90nm 20MHz fully nonvolatile microcontroller for standby-power-critical applications

Recently there has been increased demand for not only ultra-low power, but also high performance, even in standby-power-critical applications. Sensor nodes, for example, need a microcontroller unit (MCU) that has the ability to process signals and compress data immediately. A previously reported 130nm CMOS and FeRAM-based MCU features zero-standby power and fast wakeup operation by incorporating FeRAM devices into logic circuits [1]. The 8MHz speed, however, was not sufficiently high to meet application requirements, and the FeRAM process also has drawbacks: low compatibility with standard CMOS, and write endurance limitations. A spintronics-based nonvolatile integrated circuit is a promising option to achieve zero standby power and high-speed operation, along with compatibility with CMOS processes. In this work, we demonstrate a fully nonvolatile 16b MCU using 90nm standard CMOS and three-terminal SpinRAM technology. It achieves 20MHz, 145μW/MHz operation with a 1V supply in the active state, and 4.5μW intermittent operation with 120ns wakeup time and 0.1% active ratio, without forwarding of re-boot code from memory. The features provide sufficiently long battery life to achieve maintenance-free sensor nodes.

A 1 Mb Nonvolatile Embedded Memory Using 4T2MTJ Cell With 32 b Fine-Grained Power Gating Scheme

A 1 Mb nonvolatile embedded memory using a four transistor and two spin-transfer-torque (STT) magnetic tunnel junction (MTJ) cell is designed and fabricated to demonstrate its zero standby power and high performance. The power supply voltages of 32 cells along a word line (WL) are controlled simultaneously by a power line (PL) driver to eliminate the standby power without impact on the access time. This fine-grained power gating scheme also optimizes the trade-off between macro size and operation power. The butterfly curve for the cell is measured to be asymmetric as predicted, enhancing the cells static noise margin (SNM) for data retention. The scaling of 1 Mb macro size is compared with that of the 6T SRAM counterpart, indicating that the former will become smaller than the latter at 45 nm technology node and beyond by moderately thinning its tunnel dielectrics (MgO) in accordance with the shrink of the MTJs cross sectional area. The operation current of the macro is also shown to be almost unchanged over generations, while that of the 6T SRAM increases exponentially due to the degradation of MOSFET off-current as the device scales.

A 3.14 um 2 4T-2MTJ-cell fully parallel TCAM based on nonvolatile logic-in-memory architecture

A four-MOS-transistor/two-MTJ-device (4T-2MTJ) cell circuit is proposed and fabricated for a standby-power-free and a high-density fully parallel nonvolatile TCAM. By optimally merging a nonvolatile storage function and a comparison logic function into a TCAM cell circuit with a nonvolatile logic-in-memory structure, the transistor counts required in the cell circuit become minimized. As a result, the cell size becomes 3.14um2 under a 90-nm CMOS and a 100-nm MTJ technologies, which achieves 60% and 86% of area reduction in comparison with that of a 12T-SRAM-based and a 16T-SRAM-based TCAM cell circuit, respectively.

VLSI implementation of deep neural networks using integral stochastic computing

The hardware implementation of deep neural networks (DNNs) has recently received tremendous attention since many applications require high-speed operations. However, numerous processing elements and complex interconnections are usually required, leading to a large area occupation and a high power consumption. Stochastic computing has shown promising results for area-efficient hardware implementations, even though existing stochastic algorithms require long streams that exhibit long latency. In this paper, we propose an integer form of stochastic computation and introduce some elementary circuits. We then propose an efficient implementation of a DNN based on integral stochastic computing. The proposed architecture uses integer stochastic streams and a modified Finite State Machine-based tanh function to improve the performance and reduce the latency compared to existing stochastic architectures for DNN. The simulation results show the negligible performance loss of the proposed integer stochastic DNN for different network sizes compared to their floating point versions.

Restructuring of memory hierarchy in computing system with spintronics-based technologies

The restructuring of todays computer memory hierarchies that are caught in a dilemma between performance gain and power reduction is one of the most promising ways to making the computers much more efficient with much less power. To this end, several possibilities of using NV memories and NV logic with spin-transfer-torque magnetic tunnel junction (STT-MTJ) as levels in new hierarchies are discussed. A new NV-SRAM cell consisting of four transistors and two MTJs (4T-2MTJ) is shown to be a promising candidate for future NV-cache memories. For NV-main memories, we propose a PFET-based 1T-1MTJ cell combined with a new sense amplifier (S/A). A new NV-latch that can be constructed in flip-flops of synchronous core circuits is proposed and the worlds fastest 600MHz operation is experimentally demonstrated.

A 600MHz MTJ-based nonvolatile latch making use of incubation time in MTJ switching

The incubation (transit) time of the perpendicular magnetic tunnel junction (MTJ) is found shorter (longer) than the in-plane MTJ. By making use of the incubation time, a new concept is proposed for MTJ/CMOS hybrid circuits that operate as fast as CMOS circuits without operation power overhead and with negligible MTJ switching error. A nonvolatile latch based on the concept is fabricated in 90nm technology to demonstrate 600MHz stable operation.

An Overview of Nonvolatile Emerging Memories— Spintronics for Working Memories

This paper reviews emerging nonvolatile random access memories (RAM) in recent years. It first benchmarks ferroelectric RAM (FeRAM), phase change RAM (PCRAM), resistive RAM (ReRAM), and spin-torque-transfer magnetic RAM (STT-MRAM), discussing each RAMs features and its applications. Then current status of spintronics developments including not only STT-MRAM but also nonvolatile logic LSI is described, which are particularly suitable for working memory applications.

High-Throughput Low-Energy Content-Addressable Memory Based on Self-Timed Overlapped Search Mechanism

This paper introduces a self-timed overlapped search mechanism for high-throughput content-addressable memories (CAMs) with low search energy. Most mismatches can be found by searching the first few bits in a search word. Consequently, if a word circuit is divided into two sections that are sequentially searched, most match lines in the second section are unused. As searching the first section is faster than searching an entire word, we could potentially increase throughput by initiating a second-stage search on the unused match lines as soon as a first-stage search is complete. The overlapped search mechanism is realized using a self-timed word circuit that is independently controlled by a locally generated control signal, reducing the power dissipation of global clocking. A 256 x 144-bit CAM is designed under in 90 nm CMOS that operates with 5.57x faster throughput than a synchronous CAM, with 38% energy saving and 8% area overhead.

Design of a 270ps-access 7-transistor/2-magnetic-tunnel-junction cell circuit for a high-speed-search nonvolatile ternary content-addressable memory

A novel 7-transistor/2-magnetic-tunnel-junction (7 T-2MTJ) cell circuit is proposed for a high-speed and compact nonvolatile ternary content-addressable memory (TCAM). Since critical path for switching in the TCAM cell circuit, which determines the performance of the TCAM, is only a single MOS transistor, switching delay of the TCAM word circuit is minimized. As a result, 270 ps of switching delay in 144-bit TCAM word circuit is achieved under a 90 nm CMOS/MTJ technology with magneto-resistance ratio of 100%, which is about two times faster than a conventional CMOS-based TCAM.