F.M. Klaassen

Accurate drain conductance modeling for distortion analysis in MOSFETs

Present compact circuit-level MOSFET models fail to accurately describe distortion effects, which is partly due to an imprecise modeling of conductance. A new MOS model has been developed which gives accurate results for distortion analysis, and incorporates a more precise description of various physical phenomena such as velocity saturation, channel length modulation, static feedback and self-heating.

Determination of the gate-voltage dependent series resistance and channel length in sub micron LDD-MOSFETs

In short channel MOSFETs the effects of series resistance become increasingly important. In this paper the limitations of two existing series resistance measurement methods [1,2] will be discussed. Because of their limitations a new measurement method will be presented for the determination of the gate voltage dependent series resistance. In addition a very useful numerical process and device simulation method to estimate the source (drain) series resistance under several bias conditions will be discussed.

Measuring the drain voltage dependent series resistance in submicron LDD MOSFET's

Though already much attention was paid to the gate-voltage dependence of the MOSFET series resistance [1] the behaviour of the drain series resistance as a function of drain bias could not be measured until now. In this paper a general measurement principle to determine the series resistance in a LDD MOSFET as a function of drain bias is developed. Measured results for a 0.7 μm device are given.