F. Masuoka

High performance CMOS surrounding gate transistor (SGT) for ultra high density LSIs

A novel transistor with compact structure has been developed for MOS devices. This transistor, whose gate electrode surrounds the pillar silicon island, reduces the occupied area for all kinds of circuits. For example, the occupied area of a CMOS inverter can be shrunk to 50% of that using planar transistors. The other advantages are steep cutoff characteristics, very small substrate bias effects, and high reliability. These features are due to the unique structure, which results in greater gate controllability and in electric field relaxation at the drain edge.<<ETX>>

A surrounding gate transistor (SGT) cell for 64/256 Mbit DRAMs

A novel three-dimensional memory cell called the surrounding gate transistor (SGT) cell has been developed for 64/256-Mb DRAMs (dynamic RAMs). In the SGT cell structure, a transfer gate and a capacitor electrode surround a pillar silicon island. Contact of the bit line is made on top of the silicon pillar. All devices for a memory cell are located in one silicon pillar. Each silicon pillar is isolated by matrixlike trenches. Therefore, there is no intercell leakage current even in small cell-to-cell spacing. The SGT cell can achieve an extremely small cell size of 1.2 mu m/sup 2/ and a large capacitance of 30 fF using a relaxed design rule of 0.5 mu m. The cell has been fabricated and its functionality confirmed.<<ETX>>

A novel circuit technology with surrounding gate transistors (SGT's) for ultra high density DRAM's

This paper describes a novel circuit technology with Surrounding Gate Transistors (SGTs) For ultra high density DRAMs. In order to reduce the chip size drastically, an SGT is employed to all the transistors within a chip. SGTs connected in series and a common source SGT have been newly developed for the core circuit, such as a sense amplifier designed by a tight design rule. Furthermore, to reduce the inherent cell array noise caused by a relaxed open bit line (BL) architecture, a noise killer circuit placed in the word line (WL) shunt region and a twisted BL architecture within the sense amplifier region combined with a novel separation sensing scheme have been newly introduced. Using the novel circuit technology, a 32.9% smaller chip size can be successfully achieved for a 64-Mb DRAM and 34.4% for a 1-Gb DRAM compared with a DRAM composed of the planar transistor without sacrificing the access time, power dissipation, and V/sub cc/ margin. Furthermore,the effectiveness of this technology is verified by using the circuit simulation of the internal main nodes such as WL and BL. >

A new flash E 2 PROM cell using triple polysilicon technology

A new Flash Electrically Erasable-PROM cell with single transistor per bit as same as conventional UV-EPROM(1) (2) and suitable for 256K bit F-E2PROM with rather conservative 2.0µm design rule is described. The cell is programmed by a channel hot carrier injection mechanism similar to EPROM. The contents of all memory cells are simultaneously erased by using field emission of electrons from a floating gate to an erase gate in a flash. The F-E2PROM cell with single transistor per bit consists of three layers of polysilicon with select transistor. (3) (4) (5) Programming is 10msec per bit as same as UV-EPROM. Good erasing characteristics is obtained with 550Å of oxide thickness between floating gate and erase gate.

A NAND structured cell with a new programming technology for highly reliable 5 V-only flash EEPROM

A programming technology is proposed to improve the endurance and read retention characteristics of NAND-structured EEPROM cells programmed by Fowler-Nordheim tunneling of electrons. Erasing and writing are accomplished uniformly over the whole channel area instead of nonuniform erasing at the drain. To achieve programming over the whole channel area, a new device structure is also proposed. The high-voltage pulses can be easily generated on a chip from a single 5-V power supply because the direct current due to the avalanche breakdown does not flow. The gate length of the memory transistor is 1.0 &mu;m. Using 1.0 &mu;m rules, the cell size per bit is 11.7 &mu;m2

A 0.67 /spl mu/m/sup 2/ self-aligned shallow trench isolation cell (SA-STI cell) for 3 V-only 256 Mbit NAND EEPROMs

An ultra high-density NAND-structured memory cell, using a new Self-Aligned Shallow Trench Isolation (SA-STI) technology, has been developed for a high performance and low bit cost 256 Mbit flash EEPROM. The SA-STI technology results in an extremely small cell size of 0.67 /spl mu/m/sup 2/ per bit, 67% of the smallest flash memory cell reported so far, by using a 0.35 /spl mu/m technology. The key technologies to realize a small cell size are (1) 0.4 um width Shallow Trench Isolation (STI) to isolate neighboring bits and (2) a floating gate that is self-aligned with the STI, eliminating the floating-gate wings. Even though the floating-gate wings are eliminated, a high coupling ratio of 0.65 can be obtained by using the side-walls of the floating gate to increase the coupling ratio. Using this self-aligned structure. A reliable tunnel oxide can be obtained because the floating gate does not overlap the trench corners, so enhanced tunneling at the trench corner is avoided. Therefore, the SA-STI cell combines a low bit cost with a high performance and a high reliability, such as the fast programming (0.2 /spl mu/sec/byte), fast erasing (2 msec), good write/erase endurance (>10/sup 6/ cycles), and excellent read disturb characteristics(>10 years). This paper describes the process technologies and the device performance of the SA-STI cell, which can be used to realize NAND EEPROMs of 256 Mbit and beyond.<<ETX>>

A reliable bi-polarity write/erase technology in flash EEPROMs

The authors describe a technology for scaling down the flash EEPROM cell, which has a conventional self-aligned double poly-Si stacked structure. It is clarified experimentally that a flash memory cell written and erased by Fowler-Nordheim (F-N) tunneling has ten times the retention time of the conventional cell, which is written by channel-hot-electron (CHE) injection and erased by F-N tunneling. This difference of data retentivity between these two write/erase (W/E) technologies is due to decreasing the thin gate oxide leakage current by bi-polarity F-N tunneling stress. This improvement in data retention becomes more pronounced as the gate oxide thickness decreases. Therefore, a bipolarity F-N tunneling WE technology, which enables a flash EEPROM cell to scale down its oxide thickness, shows promise as a key technology for realizing 16 Mb flash EEPROMs and beyond.<<ETX>>

A 4 Mb NAND EEPROM with tight programmed V/sub t/ distribution

Described is a 5-V-only 4-Mb (512K*8 b) NAND EEPROM (electrically erasable programmable ROM) with tight programmed threshold voltage (V/sub t/) distribution, controlled by a novel program-verify technique. A tight programmed V/sub t/ distribution width of 0.8 V for the 4 Mb cell array is achieved. By introducing a compact row-decoder circuit, a die size of 7.28 mm*15.31 mm is achieved using 1.0 mu m design rules. A unique twin p-well structure has made it possible to realize low-power 5 V-only erase/program operation easily and to achieve 100 K-cycle endurance. >

An accurate model of subbreakdown due to band-to-band tunneling and some applications

The authors describe a novel accurate model and numerical analysis of subbreakdown phenomena due to band-to-band tunneling in a thin-gate-oxide n-MOSFET. Subbreakdown I-V characteristics are calculated for various oxide thicknesses. The results agree with experimental results over a wide range of subbreakdown current from 10/sup -12/ A to 10/sup -6/ A. The numerical analysis based on this model has been utilized to suppress the subbreakdown current. It is concluded that the model can be utilized for the design of thin-gate-oxide devices. >

An on-chip 96.5% current efficiency CMOS linear regulator using a flexible control technique of output current

This paper proposes an on-chip 96.5% current efficiency CMOS linear regulator using a flexible control technique of output current (FCOC). By the use of the FCOC technique, the proposed circuit realizes flexible output current drive according to the load current variation. Therefore, the proposed linear regulator ran supply stable output voltage using the FCOC technique. The linear regulator is fabricated by double-metal 1.2-/spl mu/m CMOS technology. The number of transistors is 46 and the die size is 0.423 mm/sup 2/. The fabricated linear regulator achieves a fluctuation of output voltage less than 6.81 mV/sub p-p/ at a frequency of output current f(I/sub out/) ranging from 1.8 Hz to 100 MHz. Moreover, the fabricated on-chip CMOS linear regulator can achieve 96.5% current efficiency.