R. Nakayama

A NAND structured cell with a new programming technology for highly reliable 5 V-only flash EEPROM

A programming technology is proposed to improve the endurance and read retention characteristics of NAND-structured EEPROM cells programmed by Fowler-Nordheim tunneling of electrons. Erasing and writing are accomplished uniformly over the whole channel area instead of nonuniform erasing at the drain. To achieve programming over the whole channel area, a new device structure is also proposed. The high-voltage pulses can be easily generated on a chip from a single 5-V power supply because the direct current due to the avalanche breakdown does not flow. The gate length of the memory transistor is 1.0 μm. Using 1.0 μm rules, the cell size per bit is 11.7 μm2

A reliable bi-polarity write/erase technology in flash EEPROMs

The authors describe a technology for scaling down the flash EEPROM cell, which has a conventional self-aligned double poly-Si stacked structure. It is clarified experimentally that a flash memory cell written and erased by Fowler-Nordheim (F-N) tunneling has ten times the retention time of the conventional cell, which is written by channel-hot-electron (CHE) injection and erased by F-N tunneling. This difference of data retentivity between these two write/erase (W/E) technologies is due to decreasing the thin gate oxide leakage current by bi-polarity F-N tunneling stress. This improvement in data retention becomes more pronounced as the gate oxide thickness decreases. Therefore, a bipolarity F-N tunneling WE technology, which enables a flash EEPROM cell to scale down its oxide thickness, shows promise as a key technology for realizing 16 Mb flash EEPROMs and beyond.<<ETX>>

An accurate model of subbreakdown due to band-to-band tunneling and some applications

The authors describe a novel accurate model and numerical analysis of subbreakdown phenomena due to band-to-band tunneling in a thin-gate-oxide n-MOSFET. Subbreakdown I-V characteristics are calculated for various oxide thicknesses. The results agree with experimental results over a wide range of subbreakdown current from 10/sup -12/ A to 10/sup -6/ A. The numerical analysis based on this model has been utilized to suppress the subbreakdown current. It is concluded that the model can be utilized for the design of thin-gate-oxide devices. >

A high-density NAND EEPROM with block-page programming for microcomputer applications

A high-density, 5-V-only, 4-Mb CMOS EEPROM with a NAND-structured cell using Fowler-Nordheim tunneling for programming is discussed. The block-page mode is utilized for high-speed programming and easy microprocessor interface. On-chip test circuits for shortening test time and for evaluating cell characteristics yield highly reliable EEPROMs. The NAND EEPROM has many applications for microcomputer systems that require small size and large nonvolatile storage systems with low power consumption. >

A 2.3 mu m/sup 2/ memory cell structure for 16 Mb NAND EEPROMs

A NAND structure memory cell with 2.2*1.05 mu m/sup 2/ size per bit, based on a 0.6 mu m design rule, has been developed for 16 Mb flash EEPROMs. The cell size is about 64% of the smallest 16 Mb EPROM cell so far reported. An extremely small cell can be realized by the following technologies: (1) newly developed 0.3 mu m space self-aligned stacked gate patterning, (2) a NAND structured cell array which contains 16 memory transistors in series, and (3) high-voltage field isolation technology used to isolate neighboring bits. The first and second technologies reduce the length of the cell by 67.6% compared with the conventional NAND structured cell using the same design rule, while the third technology reduces the width by 84.6%.<<ETX>>

Extended data retention characteristics after more than 10/sup 4/ write and erase cycles in EEPROMs

Improvements in data retention characteristics of a FETMOS cell which has a self-aligned double poly-Si stacked structure are discussed. The improvement results from the use of a uniform write and erase technology. Experiments show that a gradual detrapping of electrons from the gate oxide to the substrate effectively suppresses data loss of the erased cell which stores positive charges in the floating gate. It is also shown that a uniform write and uniform erase technology using Fowler-Nordheim tunneling current guarantees a wide cell threshold voltage window even after 10/sup 6/ write and erase cycles. This technology realizes a highly reliable EEPROM with extended data retention characteristics.<<ETX>>

New design technology for EEPROM memory cells with 10 million write/erase cycling endurance

The authors describe a novel design technology for improving the write/erase cycling endurance characteristics for EEPROM (electrically erasable PROM) memory cells with self-aligned double polysilicon stacked structure. In this device, the source n/sup +/ region is located within the depletion region of the surface channel area when high voltage is applied to the drain with the source left floating. It is confirmed experimentally that the endurance of the newly designed memory cell using a 0.5- mu m design rule can be more than 10/sup 7/ write/erase cycles. This memory cell has superior potential for application to 64-Mb flash or 4-Mb full-featured EEPROMs.<<ETX>>

New device technologies for 5 V-only 4 Mb EEPROM with NAND structure cell

Novel device technologies for a 5-V-only EEPROM (electrically erasable programmable read-only memory) with a NAND structure cell are described. By applying half of the programming voltage to unselected bit lines and a successive programming sequence, the NAND structure cell keeps a wide threshold margin. A high-voltage CMOS process realizes reliable programming characteristics. The reliability of the cell has been confirmed experimentally. Using 1.0- mu m design rules, the unit cell area per bit is 12.9- mu m/sup 2/, which is small enough to realize a 4-Mb EEPROM.<<ETX>>