F.N. Cubaynes

Planar Bulk MOSFET s Versus FinFETs: An Analog/RF Perspective

Comparison of digital and analog figures-of-merit of FinFETs and planar bulk MOSFETs reveals an interesting tradeoff in the analog/RF design space. It is found that FinFETs possess the following key advantages over bulk MOSFETs: reduced leakage, excellent subthreshold slope, and better voltage gain without degradation of noise or linearity. This makes them attractive for digital and low-frequency RF applications around 5 GHz, where the performance-power tradeoff is important. On the other hand, in high-frequency applications, planar bulk MOSFETs are seen to hold the advantage over FinFETs due to their higher peak transconductance. However, this comes at a cost of a reduced voltage gain of bulk MOSFETs

Device and circuit-level analog performance trade-offs: a comparative study of planar bulk FETs versus FinFETs

Comparison of digital and analog figures-of-merit of FinFETs and planar bulk MOSFETs reveals an interesting trade-off in analog/RF design space. It is seen that FinFETs possess key advantages over bulk FETs for applications around 5 GHz where the performance-power trade-off is important. In case of higher frequency applications bulk MOSFETs are shown to hold the advantage on account of their higher transconductance (Gm), provided a degraded voltage gain and a higher leakage current can be tolerated

45 nm nMOSFET with metal gate on thin SiON driving 1150 /spl mu/A//spl mu/m and off-state of 10nA//spl mu/m

We demonstrate for the first time that nMOS devices with PVD TaN gate on 1.2 nm EOT SiON can be fabricated with high drive currents. On state currents of 1150 /spl mu/A//spl mu/m (I/sub off/ < 10 nA//spl mu/m) at 1.2 V and 810 /spl mu/A//spl mu/m (I/sub off/ < 10 nA//spl mu/m) at 1.0 V are among the highest ever reported. The TaN metal gate electrode allows the capacitance equivalent thickness (CET or T/sub ox-inv/) to be scaled by 0.4 nm without increasing the gate leakage. A special metal etch stopping on 1.4 nm EOT SiON has been developed resulting in gate stacks of similar reliability as poly gate electrodes. We also report on an implant into the metal gate electrode that reduces gate leakage and increases mobility.

Advanced PMOS Device Architecture for Highly-Doped Ultra-Shallow Junctions

In this paper we study the integration of Boron ultra-shallow junctions (USJ) obtained by Germanium pre-amorphization, Fluorine co-implantation and fast ramp-up and ramp-down anneals into advanced p-channel metal-oxide-semiconductor (PMOS) devices. Several integration issues associated to these USJ are investigated: short-channel effects control, implantation tilt angle influence, junction de-activation, thermal budget, silicide process. We show that remarkable PMOS device performance enhancement (Ion=450 µA/µm at Ioff=250 nA/µm for devices with Lg\cong50 nm) can be achieved when full potential of highly-active and abrupt USJ is exploited by combining it with a low thermal budget integration scheme and a low contact resistance NiSi.

Ultra-thin oxynitride gate dielectrics by pulsed-RF DPN for 65 nm general purpose CMOS applications

This paper investigates the use of pulsed-RF decoupled plasma nitridation (DPN) for the growth of oxynitride gate dielectrics for 65 nm general purpose (GP) applications. The effects of several DPN plasma parameters, base oxide thickness and post-nitridation anneal (PNA) conditions on device performance were evaluated. Significant gate leakage reduction and improved trade-off between the equivalent-oxide-thickness (EOT) and mobility, for scaled EOT, have been found in devices with oxynitrides grown from thicker base oxides and optimized DPN/PNA processing conditions. DPN oxynitrides with 1.1-1.4 nm EOT have maximum operating voltages above 0.8 V, as extrapolated for a 10 year lifetime.

Impact of downscaling and poly-gate depletion on the RF noise parameters of advanced nMOS transistors

For the first time, the effects of poly depletion on the RF noise performance of advanced CMOS transistors are reported and analyzed. Based on measurements and physical device simulations we quantify the increasing danger of poly gate depletion with downscaling on the RF noise parameters of CMOS devices. While poly depletion does not affect the minimum noise figure, it results in a degradation of the noise matching freedom for RFIC designers. This trend worsens with technology downscaling.

RFCV Test Structure Design for a Selected Frequency Range

The problems with the CV characterization on very leaky (thin) nitrided oxide are mainly due to the measurement precision and MOS gate dielectric model accuracy. By doing S-parameter measurement at RF frequency and using simple but reasonably accurate model. we can obtain proper CV curves for very thin nitrided gate dielectrics. Regarding the measurement frequency we propose a systematic method to find a frequency range in which we can select measurement frequencies for all biases to obtain a full CV curve. Moreover, we formulated the first order relationship between the measurement frequency range and the test structure design for CV characterization. With the established formulae, we redesigned the test structures and verified that the formulae can be used as a guideline for the test structure design for RFCV measurements.

Ultrashallow Junction Formation and Gate Activation in Deep-Submicron CMOS

This paper addresses the optimization of ion implantation and rapid thermal annealing for the fabrication of shallow junctions and the activation of polycrystalline silicon gates in deepsubmicron CMOS transistors. Achieving ultrashallow, low-resistance junctions was studied by combining low-energy B and As implantation with spike annealing. In addition, experiments using B doping marker superlattices were performed to identify the critical physical effects underlying dopant activation and diffusion. The combination of high ramp rates (~100 oC/s) and ~1 s cycles at temperatures as high as 1100 °C can be used to improve dopant activation without inducing significant thermal diffusion after TED has completed. MOS capacitors were used to identify the implantation and annealing conditions needed for adequate activation of the gate electrode. In comparison to the conventional recrystallized amorphous Si gates, it was found that fine-grained poly-Si allows for the use of lower processing temperatures or shorter annealing times while improving the gate activation level. The fine-grained crystal structure enhances the de-activation of B dopants in PMOS gates during the thermal treatments following gate activation. Yet, the resulting dopant loss stays within acceptable limits as verified by excellent 0.18 ?m device performance. The feasibility of spike annealing and poly-Si gate materials for 100-nm technology was proven by full integration using gate lengths down to 80 n

A manufacturable 25 nm planar MOSFET technology

The limits of scaling of planar Si MOSFET devices has been a subject of increasing interest in recent years. Consumer demand for high-performance electronic products has stimulated an ever-increasing rate of scaling of mainstream CMOS. Several results for devices with sub-50 nm gate lengths have already been reported (e.g. Timp et al., 1998; Chau et al., 2000; Wakabayashi et al., 2000) to approach the required performance values. We present here the results of study of manufacturability of sub-50 nm MOSFETs using tools routinely available for production of the 0.18 /spl mu/m CMOS generation. We show that by adapting 248 nm lithography, using nonequilibrium n-type junction formation and specially developed low-temperature processing, it is possible to manufacture devices with gate lengths as small as 15 nm. It is also confirmed that heavily pocketed devices with sub-50 nm gates show deterioration in performance.

A Manufacturable Sub-50nm PMOSFET Technology

One of the major problems during the processing of PMOS devices is the excessive diffusion of boron source and drain regions. Plasma enhanced CVD can be used to reduce the thermal budget associated with layer depositions between source/drain implants and back end. It also gives a possibility to selectively etch deposited layers to allow novel processing sequences. Here we study these possibilities and show that by using highquality PECVD depositions, we can engineer the appropriate for sub-50nm generation PMOS device architectures.