P.A. Stolk

Modeling statistical dopant fluctuations in MOS transistors

The impact of statistical dopant fluctuations on the threshold voltage V/sub T/ and device performance of silicon MOSFETs is investigated by means of analytical and numerical modeling. A new analytical model describing dopant fluctuations in the active device area enables the derivation of the standard deviation, /spl sigma/V/sub T/, of the threshold voltage distribution for arbitrary channel doping profiles. Using the MINIMOS device simulator to extend the analytical approach, it is found that /spl sigma/V/sub T/, can be properly derived from two-dimensional (2-D) or three-dimensional (3-D) simulations using a relatively coarse simulation grid. Evaluating the threshold voltage shift arising from dopant fluctuations, on the other hand, calls for full 3-D simulations with a numerical grid that is sufficiently refined to represent the discrete nature of the dopant distribution. The average V/sub T/-shift is found to be positive for long, narrow devices, and negative for short, wide devices. The fast 2-D MINIMOS modeling of dopant fluctuations enables an extensive statistical analysis of the intrinsic spreading in a large set of compact model parameters for state-of-the-art CMOS technology. It is predicted that V/sub T/-variations due to dopant fluctuations become unacceptably large in CMOS generations of 0.18 /spl mu/m and beyond when the present scaling scenarios are pursued. Parameter variations can be drastically reduced by using alternative device designs with ground-plane channel profiles.

Transient enhanced diffusion of boron in Si

On annealing a boron implanted Si sample at similar to800 degreesC, boron in the tail of the implanted profile diffuses very fast, faster than the normal thermal diffusion by a factor 100 or more. ...

A Comparison of Spike, Flash, SPER and Laser Annealing for 45nm CMOS

Due to integration concerns, the use of meta-stable junction formation approaches like laser thermal annealing (LTA), solid phase epitaxial regrowth (SPER), and flash annealing has largely been avoided for the 90nm CMOS node. Instead fast-ramp spike annealing has been optimised along with co-implantation to satisfy the device requirements, often with the help from thin offset spacers. However for the 65nm and 45nm CMOS node it is widely accepted that this conventional approach will not provide the required pMOS junctions, even with changes in the transistor architecture. In this work, we will compare junction performance and integratablity of fast-ramp spike, flash, SPER and laser annealing down to 45nm CMOS. The junction depth, abruptness and resistance offered by each approach are balanced against device uniformity, deactivation and leakage. Results show that the main contenders for the 45nm CMOS are SPER and flash annealing – but both have to be rigorously optimised for regrowth rates, amorphous positioning and dopant and co-implant profiles. From the two, SPER offers the best junction abruptness ( 4E20at/cm3) and less transistor modifications. As expected, Ge and F co-implanted spike annealed junctions do not reach the 45nm node requirements. For full-melt LTA, poly deformation on isolation can be reduced but geometry effects result in unacceptable junction non-uniformity.

Gate-workfunction engineering using poly-(Si,Ge) for high-performance 0.18 /spl mu/m CMOS technology

We show that poly-SiGe can be readily integrated as a gate material into an existing CMOS technology to achieve significant increase in the transistor performance. In order to preserve the standard salicidation scheme, a buffer poly-Si layer is introduced in the gate stack. PMOST channel profiles are optimized to account for the change of the gate workfunction. High-performance CMOS 0.18 /spl mu/m devices are manufactured using p- and n-type poly-Si/Si/sub 0.8/Ge/sub 0.2/ gates.

Optimisation of Junctions formed by Solid Phase Epitaxial Regrowth for sub-70nm CMOS

For the 70nm CMOS node, it is anticipated that conventional implantation and spike annealing approaches, even with pre-amorphisation and co-implantation, are unlikely to provide pMOS junctions consistent with the ITRS requirements. Here the junction performance is limited by equilibrium solid solubility. As laser annealing and in-situ doping techniques currently have unsolved integration problems, there is a renewed interest in using solid phase epitaxial regrowth (SPER) to form ultra-shallow metastable junctions. Such junctions have the potential to have an active dopant profile similar to the as-implanted profile. This offers above equilibrium solid solubility and abrupt profiles compatible with 70nm and even 45nm nodes. However there are concerns about residual defects, deactivation, diffusion and uniformity. In this paper we show how the Ge, F and B implant and SPER anneal can be optimised for abrupt, uniform and highly activated B junctions. There is latitude for higher doses and energies than conventional implants, however results show that this may lead to clustering causing enhanced deactivation and reduced mobility. We give attention to the probing issues involved in characterising partially annealed junctions. With this approach, p-type junctions having a sheet resistance of 265 ohms/sq and depth of 22nm are realised which are compatible with 70nm and potentially 45nm CMOS nodes.

Low Energy Implantation and Transient Enhanced Diffusion: Physical Mechanisms and Technology Implications

Low energy implantation is currently the most promising option for shallow junction formation in the next generations of silicon CMOS technology. Of the dopants that have to be implanted, boron is the most problematic because of its low stopping power (large penetration depth) and its tendency to undergo transient enhanced diffusion and clustering during thermal activation. This paper reports recent advances in our understanding of low energy B implants in crystalline silicon. In general, satisfactory source-drain junction depths and sheet resistances are achievable down to 0.18 micron CMOS technology without the need for implantation of molecular species such as BF 2 . With the help of defect engineering it may be possible to reach smaller device dimensions. However, there are some major surprises in the physical mechanisms involved in implant profile formation, transient enhanced diffusion and electrical activation of these implants, which may influence further progress with this technology. Some initial attempts to understand and model these effects will be described.

Optimizing p-type ultra-shallow junctions for the 65 nm CMOS technology node

The limits of using B or BF2 alone in forming ultrashallow junctions have been reached for the 90 nm CMOS generation. In this paper we evaluate the use of Ge and F co-implants to extend conventional implantation and spike anneal to the 65 nm CMOS technology node. In this work we show that the F co-implant can improve the abruptness of the B junction, while the single Ge usually degrades it. The use of Ge co-implanted with F gives the best junction abruptness - less than 5nm/decade. The best trade-off between junction depth (Xj) and sheet resistance (Rsheet) is achieved by deep Ge pre-amorphization and deep co-implantation of F. A comparison between slow and fast ramp-up is made. Significant improvement for the junction activation, its depth and abruptness is obtained by spike anneal with fast ramp-up for B junctions with Ge and F co-implantation.

Impact of Source/drain Implants on Threshold Voltage Matching in Deep Sub-micron CMOS Technologies

A new mechanism causing deterioration of the threshold voltage matching performance of MOSFETs is described. We demonstrate that this effect depends on several fundamental CMOS device architecture aspects such as the source/drain implant energies, the gate layer thickness, a gate top oxide layer thickness and the poly-silicon gate morphology. It is concluded that penetration of a small (fluctuating) fraction of the LDD and HDD source drain implants through the gate can be responsible for severe degeneration of the matching performance of deep sub-micron CMOS technologies.

Cluster ripening and transient enhanced diffusion in silicon

Abstract Transient enhanced diffusion of boron marker layers following silicon ion implantation shows a complex behavior as a function of annealing temperature and time. In the initial phase of ripening, small clusters with low binding energy give rise to an extremely large interstitial supersaturation (∼106–107 at 600°C). As the clusters ripen into {113} defects the supersaturation drops to a level which remains almost constant with time until the {113} defects have dissolved. By inverse modeling of the Ostwald ripening process, values are extracted for several basic physical parameters: the energy barrier for boron-interstitial association, the dissociation energy Ediss of the migrating boron-interstitial species, and the interstitial self-diffusion product. The data are consistent with recent ab initio predictions that the migrating boron species is a boron-interstitial pair. Analysis of the detailed time evolution of TED allows us to extract Ediss for silicon clusters and {113} defects as a function of defect size, n. We find strong oscillations on Ediss in the size range 2

A 0.13 /spl mu/m poly-SiGe gate CMOS technology for low-voltage mixed-signal applications

We present here a novel approach to CMOS fabrication based on advanced lateral channel doping profiling technique coupled to gate workfunction engineering. The performance of this technology for both digital and analog applications is evaluated in detail to illustrate that it satisfies the requirements for mixed digital-analog circuitry. The use of asymmetric source/drain lateral profiles proves to be especially beneficial to analog applications.