C.J.J. Dachs

A new compact model for junctions in advanced CMOS technologies

We present a new compact model for the junction capacitances and leakage currents in deep-submicron CMOS technologies. The model contains Shockley-Read-Hall generation/recombination, trap-assisted tunneling, band-to-band-tunneling, and avalanche breakdown. It has been validated for a wide range of bias and temperature, for NMOS and PMOS junctions, and for different CMOS generations

45 nm nMOSFET with metal gate on thin SiON driving 1150 /spl mu/A//spl mu/m and off-state of 10nA//spl mu/m

We demonstrate for the first time that nMOS devices with PVD TaN gate on 1.2 nm EOT SiON can be fabricated with high drive currents. On state currents of 1150 /spl mu/A//spl mu/m (I/sub off/ < 10 nA//spl mu/m) at 1.2 V and 810 /spl mu/A//spl mu/m (I/sub off/ < 10 nA//spl mu/m) at 1.0 V are among the highest ever reported. The TaN metal gate electrode allows the capacitance equivalent thickness (CET or T/sub ox-inv/) to be scaled by 0.4 nm without increasing the gate leakage. A special metal etch stopping on 1.4 nm EOT SiON has been developed resulting in gate stacks of similar reliability as poly gate electrodes. We also report on an implant into the metal gate electrode that reduces gate leakage and increases mobility.

A 0.13 /spl mu/m poly-SiGe gate CMOS technology for low-voltage mixed-signal applications

We present here a novel approach to CMOS fabrication based on advanced lateral channel doping profiling technique coupled to gate workfunction engineering. The performance of this technology for both digital and analog applications is evaluated in detail to illustrate that it satisfies the requirements for mixed digital-analog circuitry. The use of asymmetric source/drain lateral profiles proves to be especially beneficial to analog applications.

Advanced PMOS Device Architecture for Highly-Doped Ultra-Shallow Junctions

In this paper we study the integration of Boron ultra-shallow junctions (USJ) obtained by Germanium pre-amorphization, Fluorine co-implantation and fast ramp-up and ramp-down anneals into advanced p-channel metal-oxide-semiconductor (PMOS) devices. Several integration issues associated to these USJ are investigated: short-channel effects control, implantation tilt angle influence, junction de-activation, thermal budget, silicide process. We show that remarkable PMOS device performance enhancement (Ion=450 µA/µm at Ioff=250 nA/µm for devices with Lg\cong50 nm) can be achieved when full potential of highly-active and abrupt USJ is exploited by combining it with a low thermal budget integration scheme and a low contact resistance NiSi.

Ultra-thin oxynitride gate dielectrics by pulsed-RF DPN for 65 nm general purpose CMOS applications

This paper investigates the use of pulsed-RF decoupled plasma nitridation (DPN) for the growth of oxynitride gate dielectrics for 65 nm general purpose (GP) applications. The effects of several DPN plasma parameters, base oxide thickness and post-nitridation anneal (PNA) conditions on device performance were evaluated. Significant gate leakage reduction and improved trade-off between the equivalent-oxide-thickness (EOT) and mobility, for scaled EOT, have been found in devices with oxynitrides grown from thicker base oxides and optimized DPN/PNA processing conditions. DPN oxynitrides with 1.1-1.4 nm EOT have maximum operating voltages above 0.8 V, as extrapolated for a 10 year lifetime.

Impact of downscaling and poly-gate depletion on the RF noise parameters of advanced nMOS transistors

For the first time, the effects of poly depletion on the RF noise performance of advanced CMOS transistors are reported and analyzed. Based on measurements and physical device simulations we quantify the increasing danger of poly gate depletion with downscaling on the RF noise parameters of CMOS devices. While poly depletion does not affect the minimum noise figure, it results in a degradation of the noise matching freedom for RFIC designers. This trend worsens with technology downscaling.

Modeling Facet Formation for Non-Planar Thermal Oxidation of Silicon

A model for simulating 2D and 3D oxide shape for oxidation of non-planar silicon surfaces is presented. The model is based on an idea that the stress dependence of the reaction rate can be anisotropic with respect to the crystallographic orientation of silicon surface. It describes facet formation, observed in liner oxide at the corners of STI (Shallow Trench Isolation). It is also necessary to describe the shape of top STI corner which is critical in determining the MOSFET leakage.

RPN Oxynitride Gate Dielectrics for 90 nm Low Power CMOS Applications

This paper investigates the use of RPN-based oxynitride gate dielectrics for 90 nm Low Power (LP) CMOS applications. Several recipes have been developed to optimise the gate dielectric for targeted EOT, high mobility and improved EOT uniformity. Compared to conventional furnace oxynitride, significant gate leakage reduction has been found in devices with plasma nitrided oxides. This enabled reaching the spec for the IOFF current of 20 pA/ µm and improve the ION-IOFF trade-off. The ION current obtained at 1.2 V for NMOS and PMOS devices is 427 µA/µ m( at IOFF =16 pA/µm) and 170 µA/µ m( at I OFF =16 pA/µm), respectively. The obtained results are among the best values reported in the literature.

A manufacturable 25 nm planar MOSFET technology

The limits of scaling of planar Si MOSFET devices has been a subject of increasing interest in recent years. Consumer demand for high-performance electronic products has stimulated an ever-increasing rate of scaling of mainstream CMOS. Several results for devices with sub-50 nm gate lengths have already been reported (e.g. Timp et al., 1998; Chau et al., 2000; Wakabayashi et al., 2000) to approach the required performance values. We present here the results of study of manufacturability of sub-50 nm MOSFETs using tools routinely available for production of the 0.18 /spl mu/m CMOS generation. We show that by adapting 248 nm lithography, using nonequilibrium n-type junction formation and specially developed low-temperature processing, it is possible to manufacture devices with gate lengths as small as 15 nm. It is also confirmed that heavily pocketed devices with sub-50 nm gates show deterioration in performance.

Pre-amorphization and co-implantation suitability for advanced PMOS devices integration

now at Philips Semiconductors, Crolles, France