F. R. Grull

Visualization and Quantitative Analysis of Reconstituted Tight Junctions Using Localization Microscopy

Tight Junctions (TJ) regulate paracellular permeability of tissue barriers. Claudins (Cld) form the backbone of TJ-strands. Pore-forming claudins determine the permeability for ions, whereas that for solutes and macromolecules is assumed to be crucially restricted by the strand morphology (i.e., density, branching and continuity). To investigate determinants of the morphology of TJ-strands we established a novel approach using localization microscopy. TJ-strands were reconstituted by stable transfection of HEK293 cells with the barrier-forming Cld3 or Cld5. Strands were investigated at cell-cell contacts by Spectral Position Determination Microscopy (SPDM), a method of localization microscopy using standard fluorophores. Extended TJ-networks of Cld3-YFP and Cld5-YFP were observed. For each network, 200,000 to 1,100,000 individual molecules were detected with a mean localization accuracy of ∼20 nm, yielding a mean structural resolution of ∼50 nm. Compared to conventional fluorescence microscopy, this strongly improved the visualization of strand networks and enabled quantitative morphometric analysis. Two populations of elliptic meshes (mean diameter <100 nm and 300–600 nm, respectively) were revealed. For Cld5 the two populations were more separated than for Cld3. Discrimination of non-polymeric molecules and molecules within polymeric strands was achieved. For both subtypes of claudins the mean density of detected molecules was similar and estimated to be ∼24 times higher within the strands than outside the strands. The morphometry and single molecule information provided advances the mechanistic analysis of paracellular barriers. Applying this novel method to different TJ-proteins is expected to significantly improve the understanding of TJ on the molecular level.

Accelerating Image Analysis for Localization Microscopy with FPGAs

Localization microscopy enhances the resolution of fluorescence light microscopy by about an order of magnitude. Single fluorescent molecules act as switchable markers. Their detected signals can be fitted with a two-dimensional Gaussian distribution and thus located with sub-pixel resolution. In this paper we propose that these fits can be done by calculating the center of mass instead of an iterative least-square fit without loosing precision. The simplification of the algorithm leads to an acceleration of more than a factor of 100 and enables an FPGA implementation with an additional performance boost by a factor of 225. Our findings allow the real-time processing of current and future image data rates in localization microscopy.

Increasing design changeability using dynamical partial reconfiguration

Recent questions of physics lead to the construction of high energy physic experiments like ALICE at CERN or CBM at FAIR. Since research goals evolve over the lifetime of such experiments, it must be possible to change the functionality of filters and other processing units after their installation. Hence, it has been common for years, to utilize reconfigurable FPGAs for data filtering and data forwarding. This paper illustrates how a dynamical partial reconfiguration framework can help to significantly increase the changeability of these FPGAs regarding typical data acquisition applications and algorithms, which finally leads to a better capacity utilization and thus enables cost and energy savings.

Parallel hardware objects for dynamically partial reconfiguration

Many of todaypsilas software-to-hardware compiler projects try to find dataflow parallelism in a sequential program description and use it to generate parallel running hardware components. In this paper we present a new possibility to do a parallel description based on the combination of object-oriented programming and dynamically partial reconfiguration. Our compiler translates software objects directly to hardware objects, which are running in parallel and can be instantiated and removed dynamically. Furthermore, we focus on parallel inter object communication which allows the hardware objects to communicate in parallel.

Biomedical image processing and reconstruction with dataflow computing on FPGAs

Increasing chip sizes and better programming tools have made it possible to increase the boundaries of application acceleration with FPGAs. Two applications, localization microscopy and electron tomography, are presented in the authors PhD thesis and summarized in this paper. Both have been ported from imperative languages to the dataflow paradigm that maps well onto long processing pipelines in custom hardware. The results show that an acceleration of 200 compared to an Intel i5 450 CPU for localization microscopy, and an acceleration of 5 over an Nvidia Tesla C1060 for electron tomography while maintaining full accuracy. The main challenge arose from the need to fully understand and re-write most of the imperative source in a form suitable for dataflow computing.

High-Level Data Flow Description of FPGA Firmware Components for Online Data Preprocessing

FPGA firmware for detector read-out is commonly described with VHDL or Verilog. Data processing on the algorithmic level is a complex task in these languages and creates code that is hard to maintain. There are high level description frameworks available that simplify the implementation of processing algorithms. A sample implementation of an existing algorithm and the comparison with its VHDL equivalent show promising results for future online preprocessing systems. Field Programmable Gate Arrays (FPGAs) are widely used in high energy physics detector read-out chains due to their flexibility. The protocols and interfaces are usually implemented with hardware description languages like VHDL or Verilog. With FPGAs getting bigger and faster they become more and more suitable for performing complex data processing tasks. This can reduce the data volume and significantly ease demands on later software based processing steps. The drawback of the commonly used hardware description languages is that they are mostly working on the Register Transfer Level. This is perfect for high performance protocol and low level interface implementations. However, using these languages to implement data processing on an algorithmic level requires experienced developers and usually involves customized IP cores and latency matching of components. This creates a rather complex and static design. There are several high level hardware description frameworks available that provide their own languages to describe data processing steps on an algorithmic or data flow level. Some of them also come with an own framework including building blocks for PCIe or DRAM interfaces. This significantly speeds up the development compared to a description in plain VHDL or Verilog. The underlying framework of this work is made by Maxeler Technologies. The platform generates a pipelined version of the algorithm after its data flow graph has been described in a Java-like programming language [1]. The compiler manages the scheduling of the design, inserts latencies in the generated pipelines wherever needed to keep the data in sync, and instantiates interfaces to PCIe or DRAM if required. A software environment with a device driver and C API provides easy to use stream interfaces to the hardware. The compiler translates the data flow description into VHDL code which is then run through the vendor tools. The algorithm described in this way is the FastClusterFinder that was used as a VHDL core in the readout of the ALICE Time Projection Chamber during LHC run pe-