Fazrena Azlee Hamid

Analysis of Programme Outcomes achievement for Electrical Engineering programmes in UNITEN

In Outcome-Based Education approach, Programme Outcomes (PO) is a series of technical and non-technical skills that a graduate from an institution should acquire prior to graduation. The qualities in the PO are usually closely related to the training that the student has gone through. The attainment of PO must be tracked at every semester and corrective actions must be implemented if the attainment does not meet the performance criterion that has been set. This implies a need for a continuous quality improvement (CQI) process for PO attainment. This paper presents the analysis of PO achievement based on students achievement in formal assessments for core subjects in the Bachelor of Electrical Power Engineering (BEPE) and Bachelor of Electrical and Electronics Engineering (BEEE) programmes in UNITEN for four semesters from Semester 1, 2007/2008 to Semester 2, 2008/2009. In general, all POs are attained by both programmes. However, it was observed that with the current performance criteria a decline in soft skills PO achievement was observed. Hence, a new PO attainment strategy was devised and a new performance criterion has been set. This paper aims to highlight the CQI processes in place to analyze the BEPE and BEEE Programme Outcomes attainment.

Analyze and optimize the silicide thickness in 45nm CMOS technology using Taguchi method

Taguchi method was used to analyze the experimental data in order to get the optimum average of silicide thickness in 45nm devices. The virtually fabrication of the devices was performed by using ATHENA module. While the electrical characterization of the devices was implemented by using ATLAS module. These two modules were used as design tools and helps to reduce design time and cost. In this paper, both modules and Taguchi method was combined to aid in design and optimizer the process parameters. There are four process parameters (factors), namely Halo Implantation, Source/Drain (S/D) Implantation, Oxide Growth Temperature and Silicide Anneal temperature. These factors were varied for 3 levels to perform 9 experiments. Threshold voltage (VTH) results were used as the evaluation variables. Then, the results were subjected to the Taguchi method for determine the optimal process parameters and to produce predicted values. The predicted values of the process parameters were successfully verified with ATHENA and ATLASs simulator. The results show that the average of silicide thickness after optimizations approaches was 30.66nm and 30.58nm for NMOS and PMOS devices respectively. In this research, Halo Implantation was identified as one of the process parameters that has the strongest effect on the response characteristics. While the S/D Implantation was identified as an adjustment factor to get the nominal values of threshold voltage for PMOS and NMOS devices equal to −0.1501V and +0.150047V respectively.

Cobalt silicide and titanium silicide effects on nano devices

This paper describes growth process of the two silicide Sub-nanometer devices and the different effects of having cobalt silicide and titanium silicide on a Sub-nanometer CMOS devices. On the top of CMOS device gate, metal silicide is developed on-top of the polysilicon to produce an ohmic contact between the polysilicon and aluminum wire. The ohmic contact should be better compared to metal-polysilicon borders. This silicide has been widely used to reduce resistance of polysilicon gates. Metal silicides such as titanium silicide (TiSi2), tungsten salicide (WSi2), cobalt salicide (CoSi2) andnickel salicide (NiSi2) are widely used for this purpose. These metals react with polysilicon, to form metal silicide layer that possesses better physical and electrical properties to interface with aluminium. The silicide need to be optimally annealed in order to obtain a good ratio of metal silicide to silicon in the gate structure Titanium silicide is formed by depositing PVD Ti on silicon substrates followed by annealing process. Anneals were carried out in an N2 ambient and resulted in a thin TiN layer on the silicide surface. For cobalt cilicide, a CVD cobalt layer was deposited on-top silicon at 450°C, and after annealing the structure, Co2Si phase was formed. And at 800°C the high resistivity CoSi phase formed. As we continued to increase the anneal temperature to 950°C, CoSi2 layer is formed. The high temperature required to form a silicide and the non existence of the Co2Si phase are attributed to the oxide at the interface. It is found that cobalt silicide grew faster and deeper to the silicon, thus saving a lot of time and cost. The succeding experiments also show that cobalt silicide has better electrical properties such as sheet resistance, capacitance and electron mobility. The transistor fabrication process was simulated by using Silvaco ATHENA module and the resulting electrical characterization was simulated using ATLAS module

Effect of process parameter variations on threshold voltage in 45nm NMOS device

Taguchi method was used to optimize of the effect process parameter variations on threshold voltage in 45nm NMOS device. In this paper, there are four process parameters (factors) were used, which are Halo Implantation, Source/Drain (S/D) Implantation, Oxide Growth Temperature and Silicide Anneal temperature. The virtual fabrication of the devices was performed by using ATHENA module. While the electrical characterization of the devices was implemented by using ATLAS module. These two modules were combined with Taguchi method to aid in design and optimizer the process parameters. Threshold voltage (VTH) results were used as the evaluation variables. The results were then subjected to the Taguchi method to determine the optimal process parameters and to produce predicted values. The predicted values of the process parameters were then successfully verified with ATHENA and ATLASs simulator. In this research, oxide growth temperature was identified as one of the process parameters that has the strongest effect on the response characteristics. While the S/D Implantation was identified as adjustment factor to get the nominal values of threshold voltage for NMOS device equal to 0.15V.

Characterization and optimizations of silicide thickness in 45nm pMOS device

The characteristics of high performance 45nm pMOS devices based on International Technology Roadmap for Semiconductor (ITRS) have been studied using ATHENA and ATLASs simulator. There are four factors were varied for 3 levels to perform 9 experiments. The factors are halo implantation, Source/Drain (S/D) implantation, oxide growth temperature and silicide anneal temperature. In this paper, Taguchi Method was used to analyze the experimental data in order to get the optimum solutions for these factors. The silicide on the poly-Si gate electrode has been used to reduce the gate electrode resistance. The result shows that the threshold voltage (VTH) value is −0.1501 Volts. The value is exactly same with ITRS prediction. This shows that Taguchi Method is a very useful tool to predict the optimum solution in finding the 45nm pMOS fabrication recipes with appropriate VTH value. The result also shows that the average of silicide thickness after optimizations approaches is 30.12nm.

Teaching introductory level VLSI Design course to UNITEN undergraduate students

VLSI design is a field which involves integrating very small devices on a very small piece of substrate. In Universiti Tenaga Nasional (UNITEN), an introduction to this field is offered as an elective course in the Bachelor of Electrical and Electronics Engineering program. The course is aimed to provide students a solid foundation in digital integrated circuit (IC) design. The content of this paper focuses mainly on course development, teaching methodologies and course assessment. The course outcomes are properly presented and they are reflected through discussions on the course contents and course assessment such as project, assignments and examinations.

Performance analysis of CMOS-memristor hybrid ring oscillator Physically Unclonable Function (RO-PUF)

The memristor is the fourth fundamental passive circuit element, whereas the Physically Unclonable Function (PUF) is a relatively new hardware-based security primitive. PUFs are unclonable due to manufacturing process variations Thus, PUFs are said to have a fingerprint that is unique to each PUF which can be used for security purposes. In this paper, the memristor is applied into a PUF, where a CMOS-memristor hybrid ring oscillator PUF (RO-PUF) is introduced. The proposed RO-PUF circuit is analyzed in terms of uniqueness, uniformity, and bit-aliasing, which were found to be 48.57%, 51.43%, and 51.43%, respectively. The performance metrics results were close to the ideal value of 50%, indicating that the proposed PUF functions well. In future research, this CMOS-memristor RO-PUF is to be used in many hardware security applications and protocols.

Analyze of input process parameter variation on threshold voltage in 45nm n-channel MOSFET

In this paper, Taguchi method was used to analyze of input process parameters variations on threshold voltage (VTH) in 45nm n-channel Metal Oxide Semiconductor device. The orthogonal array, the signal-to-noise ratio, and analysis of variance are employed to study the performance characteristics of a device. In this paper, there are eight process parameters (control factors) were varied for 2 and 3 levels to performed 18 experiments. Whereas, the two noise factors were varied for 2 levels to get four readings of VTH for every row of experiment. VTH results were used as the evaluation variable. This work was done using TCAD simulator, consisting of a process simulator, ATHENA and device simulator, ATLAS. These two simulators were combined with Taguchi method to aid in design and optimize the process parameters. In this research, S/D implant energy was identified as one of the process parameter that has the strongest effect on the response characteristics. While the halo implant dose was identified as an adjustment factor to get the nominal values of VTH for NMOS device equal to 0.289V at tox= 1.06nm.

Impact of HALO structure on threshold voltage and leakage current in 45nm NMOS device

In this paper, we investigate the impact of process parameter like halo structure on threshold voltage (VTH) and leakage current (ILeak) in 45nm NMOS device. The settings of process parameters were determined by using Taguchi experimental design method. Besides halo implant, the other process parameters which used were Source/Drain (S/D) implant and oxide growth temperature. This work was done using TCAD simulator, consisting of a process simulator, ATHENA and device simulator, ATLAS. These two simulators were combined with Taguchi method to aid in design and optimize the process parameters. In this research, the most effective process parameters with respect to threshold voltage and leakage current are oxide growth temperature (71%) and S/D implant dose (47%) respectively. Whereas the second ranking factor affecting VTH and ILeak are halo implant tilt (15%) and halo implant dose (35%) respectively. As conclusions, S/D implant dose and oxide growth temperature have the strongest effect on the response characteristics. The results show that the VTH for NMOS device equal to 0.150V at tox= 1.1nm. The results show that ILeak after optimizations approaches is 51.8µA/µm.

Memristor-based arbiter Physically Unclonable Function (APUF) with multiple response bits

The memristor, short for memory resistor, is the fourth fundamental passive circuit element, whereby it can remember the resistance based on the last applied voltage. The memristor is used in the Physically Unclonable Function (PUF), which has potential for hardware security. To improve the performance of the memristor-based arbiter PUF, two modifications were made on the design, which are extracting multiple response bits from various stages in the delay paths in order to increase resistance against attacks, and using the SR latch rather than the D flip-flop as the arbiter because of better input-to-output path symmetry in the SR latch to minimize repsonse bias as well as circuit size and overhead. The proposed memristor-based APUF were simulated with two, three, and four memristors per stage. The memristor-based APUF performance were analyzed in terms of uniqueness, uniformity, and bit-aliasing, where the average values obtained were 49.32%, 53.21%, and 53.21%, respectively. The proposed memristor-based APUF performs well as expected.