F. Van de Wiele

Modeling of ultrathin double-gate nMOS/SOI transistors

An analytical model valid near and below threshold is derived for double-gate nMOS/SOI devices. The model is based on Poissons equation, containing both the doping impurity charges and the electron concentration. An original assumption of the constant difference between surface and mid-film potentials is successfully introduced. The model provides explicit expressions of the threshold voltage and threshold surface potential, which may no longer be assumed to be pinned at the limit of strong inversion, and demonstrates the nearly ideal subthreshold slope of ultrathin double-gate SOI transistors. Very good agreement with numerical simulations is observed. Throughout the paper we give an insight into weak inversion mechanisms occurring in thin double-gate structures. >

A long-channel MOSFET model

The model describes correctly the drain current and the small signal parameters in all regions of operation, including the subthreshold regime and the saturation regime. The model contains as an approximation the charge-sheet model proposed b Brews (see ibid., vol.21, p.345, 1978). Mobility variations along the channel, resulting from the normal and lateral electric fields, can be taken into account.

High-accuracy MOS models for computer-aided design

This paper presents accurate device models (1-3 percent) to describe theI_{D}-V_{D}electrical characteristics of surface-channel PMOS transistors in strong inversion, and ion-implanted depletion-mode buried-channel PMOS transistors. The primary emphasis is an accurate description of the transverse carrier mobility with distance and normal electrical field in long-channel structures. The influence of substrate bias on carrier mobility in the surface-channel device is modeled theoretically and verified by experiment. The carrier mobility in the buried-channel devices is constant as determined experimentally with gated-diodeC-Vand conductance measurements. The modeling parameters are determined atV_{D} = 0with an automated data-acquisition micro-processor-controlled system. The models are analyzed with a least squares estimation criterion and a high degree of internal consistency is apparent from the statistical significance of the results.

Subthreshold Slope of Long-channel, Accumulation-mode P-channel Soi Mosfets

An analytical model for the subthreshold slope of the accumulation-mode p-channeI SOI MOSFET is developed. The exact solution of the equations reveals that the subthreshold swing is slightly larger (by a few percent) than that of enhancement (inversion-mode) fully depleted SOI devices. In most cases, however, the classical subthreshold slope expression developed for inversion-mode fully depleted SOI MOSFET can be used as a good approximation for accumulation-mode devices, which means that the subthreshoId swing tends to the ideal value of S-0 = kT/q 1n(10) mV/dec if the buried oxide is sufficiently thick and if the interface trap density is sufficiently low.

Threshold voltage of nonuniformly doped MOS structures

The minimum of the HF capacitance and the threshold voltage, for nonuniformly doped MOS structures, are calculated by means of an analytical model containing an adequate definition of the condition of strong surface inversion. The results obtained for profiles piling up close to the surface are in excellent agreement with those obtained by a numerical integration of Poissons equation.

Moderate inversion model of ultrathin double-gate nMOS/SOI transistors

Different 1D analytical models for the potential distribution across the silicon film of a double-gate nMOS/SOI device are proposed and compared. Models are based on a double integration of Poissons equation, which contains both the dopant impurity charges and an approximation of the minority carrier concentration. With the best approximation, a model valid from the subthreshold to the strong inversion region is obtained. It is especially useful in the moderate inversion region where classical models fail. Analytical expressions of the drain current and transconductance are provided at low V-D. The threshold voltage is extracted by the maximum transconductance change method. Good agreement with numerical simulations is achieved.

Inversion layers in abrupt /b p/-/b n/ junctions

The existence of an inversion layer near the metallurgical junction of abrupt asymmetrical /b p/-/b n/ junctions is examined by means of a simple model, valid for reverse bias. Its influence on the electric field, the potential and the capacitance of the junctions is determined and discussed.

Laser-light Absorption in Multilayers

A simple model has been derived, which accounts for the optical effects occurring during the laser processing of stacked thin films and determines the power ratio absorbed by each layer. Experimental data provided by the annealing of a Si‐SiO2‐polysilicon structure are shown to be in good agreement with theory.

Self-aligned silicon-on-insulator nano flash memory device

This paper reports on the fabrication of a silicon-on-insulator nano flash memory device based on the differential oxidation rate of silicon resulting from gradients in the arsenic doping concentration. The key processes involved are the formation of the desired arsenic doping profile, electron beam lithography and wet oxidation. The resulting device is a triangular-channel MOSFET with a nanocrystal floating gate embedded in the gate oxide. The length, width and height of the nanocrystal are 10, 10 and 20 nm, respectively. As long as the control gate voltage does not exceed +/-2V, the device behaves like a thin and narrow P-channel MOSFET. When a voltage of -5 or +5 V is applied to the control gate at room temperature, holes are injected into the floating gate or removed from it, respectively. This effect induces a persistent shift of the threshold voltage of the device, which acts as a miniature EEPROM

Current lines and accurate contact current evaluation in 2-D numerical simulation of semiconductor devices

The conservation of the total current density in semiconductor devices implies that the current derives from a vector potential. The calculation of this current potential is a dual problem of the original device simulation problem. A simple and elegant discrete method is proposed for the 2-D case, which yields the current potential for a given, numerically calculated current density. The approach is based upon a least squares principle and is consistent with the assumptions leading to the discrete formulation of the semiconductor transport equations. Accurate values of the contact currents are obtained and a simple way to generate representations of current lines becomes available. The method has the advantage that it does not require any definition of paths for the integration of current files.