P. Francis

Modeling of ultrathin double-gate nMOS/SOI transistors

An analytical model valid near and below threshold is derived for double-gate nMOS/SOI devices. The model is based on Poissons equation, containing both the doping impurity charges and the electron concentration. An original assumption of the constant difference between surface and mid-film potentials is successfully introduced. The model provides explicit expressions of the threshold voltage and threshold surface potential, which may no longer be assumed to be pinned at the limit of strong inversion, and demonstrates the nearly ideal subthreshold slope of ultrathin double-gate SOI transistors. Very good agreement with numerical simulations is observed. Throughout the paper we give an insight into weak inversion mechanisms occurring in thin double-gate structures. >

Demonstration of the potential of accumulation-mode MOS transistors on SOI substrates for high-temperature operation (150-300 degrees C)

Measurements of accumulation-mode (AM) MOS SOI transistors in the 150-300 degrees C temperature range are reported and discussed. The increases of the threshold voltage shift and off leakage current with temperature of these SOI p-MOSFETs are observed to be much smaller than their bulk equivalents. Simple models are presented to support the experimental data.<<ETX>>

Moderate inversion model of ultrathin double-gate nMOS/SOI transistors

Different 1D analytical models for the potential distribution across the silicon film of a double-gate nMOS/SOI device are proposed and compared. Models are based on a double integration of Poissons equation, which contains both the dopant impurity charges and an approximation of the minority carrier concentration. With the best approximation, a model valid from the subthreshold to the strong inversion region is obtained. It is especially useful in the moderate inversion region where classical models fail. Analytical expressions of the drain current and transconductance are provided at low V-D. The threshold voltage is extracted by the maximum transconductance change method. Good agreement with numerical simulations is achieved.

Radiation-hard design for SOI MOS inverters

The total-dose hardness of MOS integrated circuits is usually improved by increasing the hardness of the individual transistors. In this paper, we propose circuit design techniques that can further decrease the sensitivity of cells to radiation dose. This concept is applied to simple cells (inverters) produced in both thin-film SOI and gate-all-around technologies. >

Characteristics of nMOS/GAA (Gate-All-Around) Transistors neal Threshold

Simulations of, drain Current and intrinsic gate capacitances of nMOS/GAA transistors are presented and compared with experimental results. On the basis of the insight they give into the unique behaviour of these devices, new hypotheses have emerged and yielded an analytical model valid around the threshold voltage.

Comparison of self-heating effect in GAA and SOI mosfets

An analytical model is developed to estimate the effect of the scaling of the buried oxide on the heat flow in SOI devices. The heat evacuation is shown to follow the buried oxide thickness to the n-th power with -0.5 > n > -1, and it strongly depends on device dimensions. Three experimental independent evidences of reduced self-heating in GAA devices are provided and analyzed in the light of an analytical model. The advantage of the GAA structure is to replace the buried oxide below the channel by a back polysilicon gate that benefits for a much larger thermal conductivity. To achieve the same result in SOI devices, the buried oxide thickness should be reduced down to twice the gate oxide thickness, which unfortunately would also lead to a dramatic increase of source and drain parasitic capacitances. In the GAA transistor, on the contrary, source and drain regions still lie on the thick buried oxide layer such that those parasitic elements keep a low value.

Theoretical considerations for SRAM total-dose hardening

The theoretical hardness against total dose of the six-transistor SRAM cell is investigated in detail, an explicit analytical expression of the maximum tolerable threshold voltage shift is derived for two cross-coupled inverters. A numerical method is used to explore the hardness of the read and write operations. Both N- and P-channel access transistors designs are considered and their respective advantages are compared. The study points out that the radiation hardness mainly relies on the technology. Results obtained with the very robust Gate-All-Around process are finally presented. >

Comparison of hot-carrier effects in thin-film SOI and gate-all-around accumulation-mode p-MOSFETs

The advantage of symmetrical gate (GAA) SOI structures over regular SOI in the case of AM p-MOSFETs was demonstrated in several respects: suppression of a latch phenomenon, suppression of excessively high hot-electron gate currents which have been experimentally and theoretically correlated with the latch, and better resistance to hot-electron degradation due to the absence of the latch and of the vulnerable buried oxide.<<ETX>>

High Temperature Characteristics of Gaa/soi Transistors and Circuits

The GAA (Gate-All-Around) transistor is one of the latest devices of the SOI family. It presents electrical advantages as in increased transconductance and a high output impedance. It is also expected to perform very well in harsh environments like high temperatures and radiations. The motivation of this work is to verify wheter the electrical advantages still remain at temperature up to 300°C, on separate devices as well as some digital circuit components. Classical SOI and GAA structues were compared with the same starting film thickness, gate oxide, treshold voltage and design.