A. Terao

Modeling of ultrathin double-gate nMOS/SOI transistors

An analytical model valid near and below threshold is derived for double-gate nMOS/SOI devices. The model is based on Poissons equation, containing both the doping impurity charges and the electron concentration. An original assumption of the constant difference between surface and mid-film potentials is successfully introduced. The model provides explicit expressions of the threshold voltage and threshold surface potential, which may no longer be assumed to be pinned at the limit of strong inversion, and demonstrates the nearly ideal subthreshold slope of ultrathin double-gate SOI transistors. Very good agreement with numerical simulations is observed. Throughout the paper we give an insight into weak inversion mechanisms occurring in thin double-gate structures. >

Demonstration of the potential of accumulation-mode MOS transistors on SOI substrates for high-temperature operation (150-300 degrees C)

Measurements of accumulation-mode (AM) MOS SOI transistors in the 150-300 degrees C temperature range are reported and discussed. The increases of the threshold voltage shift and off leakage current with temperature of these SOI p-MOSFETs are observed to be much smaller than their bulk equivalents. Simple models are presented to support the experimental data.<<ETX>>

Moderate inversion model of ultrathin double-gate nMOS/SOI transistors

Different 1D analytical models for the potential distribution across the silicon film of a double-gate nMOS/SOI device are proposed and compared. Models are based on a double integration of Poissons equation, which contains both the dopant impurity charges and an approximation of the minority carrier concentration. With the best approximation, a model valid from the subthreshold to the strong inversion region is obtained. It is especially useful in the moderate inversion region where classical models fail. Analytical expressions of the drain current and transconductance are provided at low V-D. The threshold voltage is extracted by the maximum transconductance change method. Good agreement with numerical simulations is achieved.

Extended theoretical analysis of the steady-state linear behaviour of accumulation-mode, long-channel p-MOSFETs on SOI substrates

The different conduction mechanisms occurring in thin-film accumulation-mode SOI p-channel MOSFETs have been investigated on the basis of experimental measurements and numerical simulations under all possible steady-state conditions with low drain-source voltage. Closed-form expressions for the front-gate threshold voltage as a function of back-gate bias and associated parameters have been derived and found to be in good agreement with measurements. Our extended analysis provides a basic tool which could prove useful for new characterization, modelling or application studies of accumulation-mode SOI MOSFETs.