F.W. Sexton

Physical Mechanisms Contributing to Device "Rebound"

The physical mechanisms that produce rebound have been identified. The positive increase in threshold voltage during a bias anneal is due to annealing of oxide trapped charge. Rebound can be predicted by measuring the contribution to the threshold voltage from radiation-induced interface states immediately after irradiation.

SEU-sensitive volumes in bulk and SOI SRAMs from first-principles calculations and experiments

Large-scale three-dimensional (3D) device simulations, focused ion microscopy, and broadbeam heavy-ion experiments are used to determine and compare the SEU-sensitive volumes of bulk-Si and SOI CMOS SRAMs. Single-event upset maps and cross-section curves calculated directly from 3D simulations show excellent agreement with broadbeam cross section curves and microbeam, charge collection and upset images for 16 K bulk-Si SRAMs. Charge-collection and single-event upset (SEU) experiments on 64 K and 1 M SOI SRAMs indicate that drain strikes can cause single-event upsets in SOI ICs. 3D simulations do not predict this result, which appears to be due to anomalous charge collection from the substrate through the buried oxide. This substrate charge-collection mechanism can considerably increase the SEU-sensitive volume of SOI SRAMs, and must be included in single-event models if they are to provide accurate predictions of SOI device response in radiation environments.

Destructive single-event effects in semiconductor devices and ICs

Developments in the field of destructive single-event effects over the last 40 years are reviewed. Single-event latchup, single-event burnout, single-event gate rupture, and single-event snap-back are discussed beginning with the first observation of each effect, its phenomenology, and the development of present day understanding of the mechanisms involved.

Critical charge concepts for CMOS SRAMs

The dramatic effects of external circuit loading on the heavy-ion-induced charge-collection response of a struck transistor are illustrated using three-dimensional mixed-mode simulations. Simulated charge-collection and SEU characteristics of a CMOS SRAM cell indicate that, in some cases, more charge call be collected at sensitive nodes from strikes that do not cause upset than from strikes that do cause upset. Computations of critical charge must take into account the time during which charge is collected, not simply the total amount of charge collected. Model predictions of the incident linear energy transfer required to cause upset agree well with measured data for CMOS SRAMs, without parameter adjustments. The results show the absolute necessity of treating circuit effects in any realistic device simulation of single-event upset (SEU) in SRAMs.

Field dependence of interface-trap buildup in polysilicon and metal gate MOS devices

The electric field dependence of radiation-induced oxide- and interface-trap charge ( Delta V/sub ot/ and Delta V/sub it/) generation for polysilicon- and metal-gate MOS transistors is investigated at electric fields (E/sub ox/) from -4.2 MV/cm to +4.7 MV/cm. If electron-hole recombination effects are taken into account, the absolute value of Delta V/sub ot/ and the saturated value of Delta V/sub it/ for both polysilicon- and metal-gate transistors are shown to follow an approximate E/sup -1/2/ field dependence for E/sub ox/>or=0.4 MV/cm. An E/sup -1/2/ dependence for the saturated value of Delta V/sub it/ was also observed for negative-bias irradiation followed by a constant positive-bias anneal. The E/sup -1/2/ field dependence observed suggests that the total number of interface traps created in these devices may be determined by hole trapping near the Si/SiO/sub 2/ interface for positive-bias irradiation or near the gate/SiO/sub 2/ interface for negative bias irradiation, though H/sup +/ drift remains the likely rate-limiting step in the process. Based on these results, a hole-trapping/hydrogen transport model-involving hole trapping and subsequent near-interfacial H/sup +/ release, transport, and reaction at the interface-is proposed as a possible explanation of Delta V/sub it/ buildup in these polysilicon- and metal-gate transistors. >

Precursor ion damage and angular dependence of single event gate rupture in thin oxides

No correlation was observed between single-event gate rupture (SEGR) and precursor damage by heavy-ion irradiation for 7-nm thermal and nitrided oxides. Precursor ion damage at biases below SEGR threshold for fluence variations over three orders of magnitude had no significant effect on SEGR thresholds. These data support a true single ion model for SEGR. A physical model based on the concept of a conducting pipe is developed that explains the empirical equation for the linear dependence of inverse critical field to rupture with LET. This model also explains the dependence of critical voltage on angle of incidence. As the oxide thickness approaches the diameter of the conducting pipe, the angular dependence of the critical voltage disappears. A model fit to the data suggests a central core diameter of 6 and 8 nm for conducting pipes induced in MOS oxides by Br and Au ions, respectively. The buildup of precursor ion damage in the oxides depends on ion species and bias during irradiation, but is not consistent with the accumulation of total ionizing dose damage. Some 5-nm oxides exhibited the characteristic high leakage current of SEGR; however, most 5-nm devices showed only soft breakdown during heavy ion exposure with electric fields up to 12 MV/cm.

Three-dimensional simulation of charge collection and multiple-bit upset in Si devices

In this paper, three-dimensional numerical simulation is used to explore the basic charge-collection mechanisms in silicon n/sup +//p diodes. For diodes on lightly-doped substrates ( >

Impact of technology trends on SEU in CMOS SRAMs

The impact of technology trends on the SEU hardness of epitaxial CMOS SRAMs is investigated using three-dimensional simulation. We study trends in SEU susceptibility with parameter variations across and within technology generations. Upset mechanisms for various strike locations and their dependence on gate-length scaling are explored. Such studies are useful for technology development and providing input for process and design decisions. An application of SEU simulation, to the development of a 0.5-/spl mu/m radiation-hardened CMOS SRAM is presented.

Total-Dose Radiation and Annealing Studies: Implications for Hardness Assurance Testing

A series of experiments covering a wide range of dose rate, bias, and annealing conditions has been performed on CMOS test transistors and 2K SRAMs. These experiments, on both hardened and commercial technologies, were designed to address hardness assurance issues associated with total-dose laboratory testing. It is demonstrated that failure dose can be a complicated function of dose rate, and that a peak in the failure-dose versus dose-rate curve generally results when there is a change in failure mode. If only one failure mode exists, then the failure-dose versus doserate curve is monotonic. Implications of proposed changes in MIL-STD-883C, Method 1019.2 are examined in light of their impact on hardness assurance. Our findings support the proposed changes of (1) keeping the time between irradiation and test less than 1 hour and (2) of a more restricted range of dose rate, i.e., 100 to 300 rad(Si)/ s. In addition, it is recommended that zero volt bias be maintained on CMOS devices between irradiation and test. Finally, techniques are presented for relating total-dose hardness as measured in the laboratory to total-dose hardness in real-world space and weapon environments.

Impact of ion energy on single-event upset

The impact of ion energy on single-event upset was investigated by irradiating CMOS SRAMs with low and high-energy heavy ions. A variety of CMOS SRAM technologies was studied, with gate lengths ranging from 1 to 0.5 /spl mu/m and integration densities from 16 Kbit to 1 Mbit. No significant differences were observed between the low and high-energy single-event upset response. The results are consistent with simulations of heavy-ion track structures that show the central fore of the track structures are nearly identical for low and high-energy ions. Three-dimensional simulations confirm that charge collection is similar in the two cases. Standard low-energy heavy ion tests are more cost-effective and appear to be sufficient for CMOS technologies down to 0.5 /spl mu/m. We discuss implications for deep submicron scaling, multiple-bit upsets, and hardness assurance.