F. Widdershoven

Real-time imaging of microparticles and living cells with CMOS nanocapacitor arrays

Platforms that offer massively parallel, label-free biosensing can, in principle, be created by combining all-electrical detection with low-cost integrated circuits. Examples include field-effect transistor arrays, which are used for mapping neuronal signals and sequencing DNA. Despite these successes, however, bioelectronics has so far failed to deliver a broadly applicable biosensing platform. This is due, in part, to the fact that d.c. or low-frequency signals cannot be used to probe beyond the electrical double layer formed by screening salt ions, which means that under physiological conditions the sensing of a target analyte located even a short distance from the sensor (∼1 nm) is severely hampered. Here, we show that high-frequency impedance spectroscopy can be used to detect and image microparticles and living cells under physiological salt conditions. Our assay employs a large-scale, high-density array of nanoelectrodes integrated with CMOS electronics on a single chip and the sensor response depends on the electrical properties of the analyte, allowing impedance-based fingerprinting. With our platform, we image the dynamic attachment and micromotion of BEAS, THP1 and MCF7 cancer cell lines in real time at submicrometre resolution in growth medium, demonstrating the potential of the platform for label/tracer-free high-throughput screening of anti-tumour drug candidates.

Investigation of the energy distribution of stress-induced oxide traps by numerical analysis of the TAT of HEs

This paper investigates by numerical modeling the results of substrate hot electron (SHE) injection experiments in virgin and stressed devices and the corresponding increase of the contribution of HEs to the gate current due to the stress-induced oxide traps. Experimental evidence of HE trap-assisted tunneling (HE TAT) is found after Fowler-Nordheim (FN) stress and SHE stress. An accurate physically based model developed to interpret the experimental results allowed us to study the energy distribution of generated oxide traps in the two different stress regimes. It is found that degradation in HE stress conditions and FN stress conditions cannot be explained by the same trap distribution. For a given stress-induced low field leakage current, a larger concentration of traps in the top part of the oxide band gap is needed to explain HE TAT after SHE stress than after FN stress. The range of trap energy where each technique is sensitive is also identified.

Explanation of SILC Probability Density Distributions With Nonuniform Generation of Traps in the Tunnel Oxide of Flash Memory Arrays

In this paper, we develop a detailed physical model to interpret the dependence of the stress induced leakage current (SILC) distributions on the nature and position of the generated defects, and we exploit it to reconsider in detail previously published experimental data on the statistical distribution of the SILC in Flash arrays. We found that a unique symmetrical spatial distribution of traps, which is rapidly decreasing from the Si-SiO2 interfaces toward the center of the oxide, can explain the oxide-thickness and stress-level dependence of the measured SILC distributions. The generation of cooperating defects with increasing stress time is also analyzed and discussed.

Experimental characterization of statistically independent defects in gate dielectrics-part I: description and validation of the model

A general statistical model to describe the generation of statistically independent defects in gate dielectrics is presented. In this first paper, the general model, suitable for different types of defects, is developed to describe the stress-induced oxide traps and the statistical properties of the trap-assisted tunneling current (TAT). With our model, it is possible to study the stress-induced leakage current statistics on large Flash memory arrays, to extract information about the number of generated defects, and to reconstruct the probability density distribution (PDD) of the gate current due to the single trap. We validated the statistical model by means of a Monte Carlo simulator developed to describe the oxide trap generation and the TAT statistics in large Flash memory arrays. In Part II, we applied the statistical model to experimental data measured on Flash memory arrays and we verified the possibility of studying, with our model, the trap generation dynamics and the PDD of the gate current produced by the single oxide defect.

A new statistical model to extract the stress induced oxide trap number and the probability density distribution of the gate current produced by a single trap

This work presents a new model to describe the statistical properties of SILC in non-volatile memory (NVM) arrays and a procedure to extract the average number of oxide traps and the probability density of the gate leakage current induced by a single trap directly from the measured histogram of SILC. The model and the extraction procedure have been validated on SILC distributions with known parameters, generated by Monte Carlo simulations, and applied to measurements performed on FLASH memory arrays. The sensitivity of the extracted parameters on the measurement resolution is discussed in detail.

Experimental evidence and statistical modeling of cooperating defects in stressed oxides [FLASH memory example]

This work reports experimental data of stress induced leakage current (SILC) extracted from large FLASH cell arrays that indicate the possible presence of two types of defects in the stressed tunnel oxides. In order to support this interpretation, both an analytical and a numerical analysis of the generation and of the current conduction of cooperating defects in large arrays of cells have been developed. Our results demonstrate that the average number of two cooperating defects increases quadratically with the average number of single defects. This is in agreement with the experimental observation that the average number of defects per cell exhibits a super-linear dependence on the duration of the stress, for heavy stress conditions. The numerical simulations qualitatively reproduce all the main features of the experiments in the memory array, thus confirming the interpretation based on cooperating defects.

Demonstration of a flash memory cell with 55 /spl Aring/ EOT silicon nitride tunnel dielectric

The authors demonstrate for the first time a flash memory cell with 55 /spl Aring/ Equivalent Oxide Thickness (EOT) silicon nitride tunnel dielectric. Their preliminary results show that this cell has good endurance characteristics and high program/erase speed. These results suggest that a high-quality JVD silicon nitride can be used as a long term solution to replace the tunnel oxide and to extend the scaling limit of tunnel dielectric in flash memory devices beyond the year 2010.

Experimental characterization of statistically independent defects in gate dielectrics-part II: experimental results on flash memory arrays

In this paper we applied the statistical model for independent defects described in Part I, to experimental data measured on Flash memory arrays. The model, developed to describe the stress-induced leakage current (SILC) statistics, allowed us to study the oxide trap generation during program/erase (P/E) stress and to extract the discrete probability distribution (DPD) of the gate current increase due to the single oxide defect. For all the analyzed nonvolatile memory arrays and for all the P/E stresses, the experimental results are consistent with the simulations carried out in Part I, thus confirming the reliability of the statistical model and of its validation procedure. Measurements on Flash cell arrays with different oxide thickness show that the number of generated oxide traps increases linearly with the number of P/E cycles in the early stage of the stress. It is shown, for the first time, that the extracted DPD of the single-trap exhibits long tails with power law dependence on the trap current and with a slope of the tail that decreases with decreasing oxide thickness. These tails are responsible for the cells with the largest SILC values in the Flash memory arrays.

Compact poly-CMP embedded flash memory

Abstract In this paper, the compact poly-CMP cell concept is presented as a good candidate for scaled embedded flash memory in future mainstream CMOS technologies. In this compact cell concept the access gate is placed next to the stacked gate transistor. The access gate has a flat top surface due to the use of chemical mechanical polishing (CMP) and therefore no depth of focus problems with the exposure of the access gate mask occur. The feasibility is proven by electrical results on mini arrays in 0.25-μm CMOS technology. Both Fowler–Nordheim tunneling and source side injection programming is possible. The program and erase degradation is investigated by endurance cycling.

Extraction of gate oxide thickness from C–V measurements

Abstract A new empirical method is described to extract the oxide thickness from C – V curves of MOS capacitors in accumulation. An analytical expression is derived for the oxide capacitance. The method is applied to MOS capacitors with metal or poly-Si gates, and with varying oxide thickness.