Fabrice Monteiro

Smart Reliable Network-on-Chip

In this paper, we present a new network-on-chip (NoC) that handles accurate localizations of the faulty parts of the NoC. The proposed NoC is based on new error detection mechanisms suitable for dynamic NoCs, where the number and position of processor elements or faulty blocks vary during runtime. Indeed, we propose online detection of data packet and adaptive routing algorithm errors. Both presented mechanisms are able to distinguish permanent and transient errors and localize accurately the position of the faulty blocks (data bus, input port, output port) in the NoC routers, while preserving the throughput, the network load, and the data packet latency. We provide localization capacity analysis of the presented mechanisms, NoC performance evaluations, and field-programmable gate array synthesis.

Designing fault-secure parallel encoders for systematic linear error correcting codes

We consider the open problem of designing fault-secure parallel encoders for various systematic linear ECC. The main idea relies on generating not only the check bits for error correction but also, separately and in parallel, the check bits for error detection. Then, the latter are compared against error detecting check bits which are regenerated from the error correcting check bits. The detailed design is presented for encoders for CRC codes. The complexity evaluation of FPGA implementations of encoders with various degrees of parallelism shows that their fault-secure versions compare favorably against their unprotected counterparts both with respect to complexity and the maximal frequency of operation. Future research will include the design of FS decoders for CRC codes as well as the generalization of the presented ideas to design of FS encoders and decoders for other systematic linear ECC like nonbinary BCH codes and Reed-Solomon codes.

A high speed encoder for recursive systematic convolutive codes

Improving the quality of service is an important target in modern multimedia applications. The main keywords defining the quality of service are the data rate and the data transmission reliability. Error correcting codes are generally employed to achieve the reliability of the data transmission. The present trend is to achieve high data rates on low-cost designs (such as FPGAs). Most of the time, parallel architectures are required to process error correcting codes with high data throughput. In this paper an effective parallel architecture is proposed for recursive convolutive systematic encoders. It is based on parallel and pipelining techniques and can be applied to non-recursive encoders. Data rates up to 693 Gbits/s can be achieved on FPGA implementations.

Fast configurable polynomial division for error control coding applications

The motivation for this paper is the need for high levels of reliability in modern telecommunication systems requiring very high data transmission rates. The search for technologically independent solutions, easy to implement on low cost and popular devices such as FPGA is an important issue. In this paper, we present a method to improve effectively the speed performance of the polynomial division performed in most error detecting and error correcting circuits. It is based on a pipeline structure for the polynomial division. Furthermore, the proposed solution is fully configurable, both from the static and the dynamic points of view. At synthesis stage, the parallelism level (size of the pipeline structure) and the maximal size of the polynomial divisor must both be chosen. Afterwards, the actual divisor can be chosen and changed while the circuit is running. The architecture proved to be very effective, as data rates up to 2.5 Gbits/s have been reached.

Real-time image encryption based chaotic synchronized embedded cryptosystems

This paper proposes a new and efficient way to deal with the chaotic synchronization for embedded hardware cryptosystems and its FPGA implementation for designing a real time image secure symmetric encryption scheme. The implementation and experimental results mapped on two Xilinx FPGA Virtex technology platforms demonstrate the feasibility and the usefulness of our secure solution. The originality of this new scheme is that it allows a low cost image encryption for embedded systems while still providing a good trade-off between performance and hardware resources. Thorough experimental tests are carried out with detailed analysis, demonstrating the high security and fast encryption speed of the new scheme while still able to resist statistical analysis attack.

Online Routing Fault Detection for Reconfigurable NoC

In this paper we present a new efficient online routing error detection approach dedicated to fault tolerant routing algorithms for the 2-D mesh reconfigurable Network-on-Chip interconnections. The main contribution is to distinguish a routing error due to switching failure from an adaptative routing decision (bypassing a faulty area or reconfigurable region in the NoC). The originality of our approach is that it can be applied to all adaptative routing based on modified turn model and well known XY algorithm, and allows the routing of messages in the networks incorporating the regions not necessarily rectangular.

Design of parallel fault-secure encoders for systematic cyclic block transmission codes

In this paper, we consider the problem of designing parallel fault-secure encoders for various systematic cyclic linear codes used in data transmission. It is assumed that the data to be encoded before transmission are stored in a fault-tolerant RAM memory system protected against errors using a cyclic linear error detecting and/or correcting code. The main idea relies on taking advantage of the RAM check bits to control the correct operation of the cyclic code encoder as well. A slightly modified encoder allows not only for encoding the transmission data stream but also, independently and in parallel, to generate the reference check bits which allow for concurrent error detection in the encoder itself. The error detection capacity proves to be effective and grants good levels of protection as shown by error injection campaigns on encoders for various standard linear cyclic error detecting and error correcting codes. Moreover, the complexity evaluation of the FPGA implementations of the encoders shows that their fault-secure versions compare favorably against the unprotected ones, both with respect to hardware complexity and the maximal frequency of operation.

Fault-Secure Interface Between Fault-Tolerant RAM and Transmission Channel Using Systematic Cyclic Codes

The problem of designing a fault-secure interface between a fault-tolerant RAM memory system and a transmission channel, both protected against errors using cyclic linear error detecting and/or correcting codes is considered. The main idea relies on using the RAM check bits to control the correct operation of the parallel cyclic code encoder, so that the whole interface has no single point of failure.

A New Efficient and Reliable Dynamically Reconfigurable Network-on-Chip

We present a new reliable Network-on-Chip (NoC) suitable for Dynamically Reconfigurable Multiprocessors on Chip systems. The proposed NoC is based on routers performing online error detection of routing algorithm and data packet errors. Our work focuses on adaptive routing algorithms which allow to bypass faulty components or processor elements dynamically implemented inside the network. The proposed routing error detection mechanism allows to distinguish routing errors from bypasses of faulty components. The new router architecture is based on additional diagonal state indications and specific logic blocks allowing the reliable operation of the NoC. The main originality in the proposed NoC is that only the permanently faulty parts of the routers are disconnected. Therefore, our approach maintains a high run time throughput in the NoC without data packet loss thanks to a self-loopback mechanism inside each router.

A self-checking hardware journal for a fault-tolerant processor architecture

We introduce a specialized self-checking hardware journal being used as a centerpiece in our design strategy to build a processor tolerant to transient faults. Fault tolerance here relies on the use of error detection techniques in the processor core together with journalization and rollback execution to recover from erroneous situations. Effective rollback recovery is possible thanks to using a hardware journal and chosing a stack computing architecture for the processor core instead of the usual RISC or CISC. The main objective of the journalization and the hardware self-checking journal is to prevent data not yet validated to be sent to the main memory, and allow to fast rollback execution on faulty situations. The main memory, supposed to be fault secure in our model, only contains valid (uncorrupted) data obtained from fault-free computations. Error control coding techniques are used both in the processor core to detect errors and in the HW journal to protect the temporarily stored data from possible changes induced by transient faults. Implementation results on an FPGA of the Altera Stratix-II family show clearly the relevance of the approach, both in terms of performance/area tradeoff and fault tolerance effectiveness, even for high error rates.