Fabrizio Lo Conte

Modeling methodology of high-voltage substrate minority and majority carrier injections

This paper presents a modeling methodology for substrate current coupling mechanisms. An enhanced model of the diode ensuring continuity of minority carriers is used to build an equivalent schematic, accounting for minority and majority carrier propagation in the substrate. For the first time a typical H-bridge structure is simulated with the proposed methodology. The parasitic current injected in the substrate by a high-voltage structure is simulated in a circuit-level simulator as well as with a finite elements method. Both are compared to measurements and show a very good agreement. The simulation resources needed by the proposed equivalent schematics are thus greatly reduced in regard to the finite element approach, offering an efficient tool for substrate modeling in smart power ICs.

Circuit Level Modeling Methodology of Parasitic Substrate Current Injection from a High-Voltage H-bridge at High Temperature

In this paper, a modeling methodology is validated based on an enhanced model of the diode, that we have developed to simulate substrate current coupling mechanisms on a typical H -bridge structure. An equivalent schematic based on an enhanced model of the diode was previously proposed to account for minority and majority carrier propagation in the substrate and implemented in Verilog-A code. In this study, the injected parasitic substrate current from high-voltage MOSFETs structure is simulated in a circuit-level simulator and with a finite element method, as well. Both are compared to measurements and confirm a very good agreement up to 400 K. Not only the simulation resources needed by the proposed equivalent schematics are greatly reduced with regard to the finite element approach, but this circuit-level modeling methodology is fully compatible with Spice-like simulations of complex ICs.

Global 2D modeling of minority and majority substrate coupled currents

This paper presents a modeling strategy to simulate 2D propagation of electrical perturbations induced by direct biasing of substrate junctions. Identifying parasitic substrate devices such as bipolar transistors reaches rapidly its limit when multiple current paths exist as in two-dimensional devices. In this work, we propose to map the substrate using only PN junctions and diffusion resistances. The model of these components has been extended in order to satisfy the majority and minority carrier continuity equation at the boundary of the component. A typical 2D parasitic structure has been simulated and the results are in good agreements with finite element simulation. The proposed approach reduces drastically the time needed to simulate a complex structure such as a whole IC substrate.

An ultra high-speed, mixed-signal emulator for solving power system dynamic equations

This paper focuses on a new pipelined processing unit architecture dedicated to mixed-signal power system emulation. Prior research in this field has proven that analog emulation overcomes the speed limits of numerical simulators with reliable accuracy. Then, a new concept based on field programmable power network system (FPPNS) has been developed in order to gain in term of flexibility. It is based on a hybrid architecture where grid equations are solved analogically and generator and load equations are solved digitally. A first platform based on a developed application specific integrated circuit has validated the concept with a 16-node topology. The present work aims to extend the size of the emulation hardware (up to 100 nodes) as well as to increase the speed. Therefore the digital equations are solved on an embedded FPGA containing four parallel pipelined processing unit which are interfaced to the analog emulator. Speed results are provided and compared with a reference numerical simulator.

Smart power IC simulation of substrate coupled current due to majority and minority carriers transports

This paper presents a new approach for substrate parasitic current simulation in smart power integrated circuit. A new compact modeling approach developed in previous work has been used to create an equivalent substrate schematic. The latter is composed of new components having the peculiarity not to fully recombine minority carrier at their boundary. By the interconnection of these special components in the electrical design, the effect of substrate current is simulated. Having this information early in the design phase will allow design optimization and reduce the risk of costly chip redesign.

9 MHz Vibrating Body FET tuning fork oscillator

A 9.4MHz micro-electromechanical oscillator based on a Vibrating Body Field Effect Transistor (VB-FET) is presented in this work. The tuning fork VB-FET used in this work provides a high quality factor of 9400 in the open-loop configuration and a low equivalent resistance. This performance makes the VB-FET an interesting candidate for fully integrated oscillator. An oscillator based on the tuning fork VB-FET is characterized.

Predictive modeling of parasitic substrate currents in high-voltage smart power IC's

This paper presents a modeling methodology for substrate current coupling mechanisms. An equivalent schematic is made using enhanced model of resistances and diodes. These enhanced components were developed in previous work and account for minority and majority carrier propagation inside the semiconductor substrates. For the first time an equivalent schematic accounting for minority carrier is validated on an integrated circuit by modeling the current coupling occurring between two high-voltage H-bridges. The results obtained from the lumped model are in very good agreement with measurements. For the first time, a simulation methodology is proposed to accurately model substrate of smart power ICs using low computer resource.

Meshing strategy of equivalent substrate schematic in SMART power IC

In this paper, a modeling methodology able to create an equivalent schematic of an High-Voltage integrated circuit is developed. The equivalent schematic is based on enhanced model of diodes and resistances, accounting for minority and majority carrier propagation at their boundary. In this work, the methodology to interconnect these elements in order to be able to model multi-dimensional current path is developed and applied to an industrial H-Bridge architecture. The coupled parasitic currents obtained with the equivalent schematic are compared against measurements and confirm that the model is accurate and can be used to estimate substrate parasitic signals.