Fadi H. Gebara

A 5.3GHz 8T-SRAM with Operation Down to 0.41V in 65nm CMOS

A 32 kb subarray demonstrates practical implementation of a 65 nm node 8T-SRAM cell for variability tolerance in highspeed caches. Ideal cell stability allows single-supply operation down to 0.41 V at 295 MHz without dynamic voltage techniques. Despite a larger cell, array area is competitive with 6T-SRAM due to higher array efficiency. With an LSDL decoder, a gated diode sense amplifier, and design tradeoffs enabled by the 8 T cell, 5.3 GHz operation at 1.2 V is achieved.

A low-voltage, chemical sensor interface for systems-on-chip: the fully-differential potentiostat

Amperometric chemical sensing systems implemented in deep-submicron processes can meet the dimensional and functional requirements for bio-implantable and remote sensing applications. The low-voltage nature of these processes, however, limits the functionality of the sensors electronic interface, the potentiostat. A new, fully-differential (FD) potentiostat that mitigates these problems is presented. The FD potentiostat was implemented in TSMCs 0.18 /spl mu/m CMOS process and experimentally verified. The circuit maintains full functionality while operating at half the supply voltage of standard architectures. Analytes of biological and environmental importance are chemically analyzed using the FD potentiostat. Results indicate that the FD potentiostat enables system-on-chip sensor technology which may one day lead to pervasive sensing.

A Fully Differential Potentiostat

Low-voltage, single-ended (SE) potentiostats are unable to detect many analytes of interest because the oxidation potentials of these analytes are greater than the voltage that the potentiostat can deliver to the electrodes. In this work, a fully-differential (FD) potentiostat is described which enables detection of a wide range of analytes using a supply voltage of 1.8 V. The FD potentiostat was implemented in TSMCs 0.18 mum CMOS process and has been verified experimentally. A theoretical discussion of the FD potentiostat is given and comparisons to SE potentiostats are provided. Biological and environmental analytes are chemically detected using the FD potentiostat.

A Top-Down Microsystems Design Methodology and Associated Challenges

An overview of microsystems technology is presented along with a discussion of the recent trends and challenges associated with its development. A typical bottom-up design methodology is described and we propose, in contrast, an efficient and effective top-down methodology. We illustrate its implementation with the development of a microsystem design that has been completed and fabricated in CMOS technology. Gaps in the tool capabilities are identified and suggestions for future directions in CAD tool support for microsystems technology are presented.

A CMOS-integrated microinstrument for trace detection of heavy metals

This paper presents a voltammetric microsystem which includes CMOS-integrated sensors, electronic interface, and data conversion circuits for enabling cost-effective, in situ detection of trace metals. The systems electronics were implemented in a 0.5 /spl mu/m, 5 V, CMOS process and occupy 36 mm/sup 2/. Single-chip integration of the system was accomplished using post-CMOS, thin-film fabrication techniques. Due to its reduced ambient noise coupling and an integrated, pseudo-differential potentiostat, this design provides the best figures of merit for detection limit, area, and power published to date for heavy-metal microinstruments. The microsystem dissipates 16 mW and has successfully detected lead at concentrations of 0.3 ppb on 3.2/spl times/10/sup -5/ cm/sup 2/ gold electrodes using subtractive anodic stripping voltammetry.

Big data text-oriented benchmark creation for Hadoop

Massive-scale Big Data analytics is representative of a new class of workloads that justifies a rethinking of how computing systems should be optimized. This paper addresses the need for a set of benchmarks that system designers can use to measure the quality of their designs and that customers can use to evaluate competing systems offerings with respect to commonly performed text-oriented workflows in Hadoop™. Additions are needed to existing benchmarks such as HiBench in terms of both scale and relevance. We describe a methodology for creating a petascale data-size text-oriented benchmark that includes representative Big Data workflows and can be used to test total system performance, with demands balanced across storage, network, and computation. Creating such a benchmark requires meeting unique challenges associated with the data size and its often unstructured nature. To be useful, the benchmark also needs to be sufficiently generic to be accepted by the community at large. Here, we focus on a text-oriented Hadoop workflow that consists of three common tasks: categorizing text documents, identifying significant documents within each category, and analyzing significant documents for new topic creation.

4.0GHz 0.18/spl mu/m CMOS PLL based on an interpolate oscillator

Phase-locked loops (PLLs) have not been the bottleneck in processor frequency performance. However, new digital circuit families, architectural improvements, and deeper pipelines have challenged this trend. In this paper, we present two novel interpolative oscillators and a phase-locked loop which is capable of clocking even the most demanding logic families. Experimental results, from a TSMC 0.18/spl mu/m process, show oscillator frequencies as high as 4.6GHz and rms jitter values of less then 1.25ps. Additionally, the PLL was able to lock to form a 4GHz output signal. These results are among the best published to date in this process.

Circuit Techniques Utilizing Independent Gate Control in Double-Gate Technologies

Independent gate control in double-gate (DG) devices enhances circuit performance and robustness while substantially reducing leakage and chip area. In this paper, we describe circuit techniques which take advantage of the independent biasing properties of symmetrical and asymmetrical DG devices in design. DG circuits at the 25-nm node are analyzed via mixed-mode numerical simulations using Taurus MEDICI. In dynamic circuits, we give examples of conditional keepers, charge sharing prevention scheme, and static keepers. A conditional keeper can dynamically achieve the optimal strength ratio between keeper and evaluation devices by utilizing the front- and backchannel currents in DG devices. A charge sharing mitigation scheme utilizing the back-gate of a logic transistor is then described. Static data retention scheme in dynamic circuits is proposed. A case study for analog applications using a voltage controlled oscillator (VCO) illustrates the specific advantages of DG devices.

Second-Generation Big Data Systems

More varied data channels, increasingly diverse analytic methods, and new deployment models-along with some fundamental technology shifts-will significantly impact the next generation of big data systems.

On-chip jitter and oscilloscope circuits using an asynchronous sample clock

We demonstrate digital circuits for measuring the jitter histograms of gigahertz clock and data signals. The circuits do not require calibration, and an asynchronous sampling technique alleviates the need for an on-chip sample clock generator with delay control. We combine measurements across swept reference voltages to create statistical clock signal and eye diagram waveforms at 6GHz and 5Gbit/s, respectively. The proposed technique produced RMS jitter measurements of 2.0ps on clock signals and 6.2ps on random data signals.