Fahim Ur Rahman

Detection and localization of faults in analog integrated circuits by utilizing the combined effect of output voltage gain and phase variation with frequency

In this paper, we have introduced a new technique based on simultaneous analysis of output voltage gain vs. frequency and phase vs. frequency for fault testing of analog integrated circuits. An Automated Test Frequency Generation method is demonstrated here to select minimum number of test frequencies as stimuli. The introduced technique is applied to three benchmark circuits and the obtained results are then compared to the results from gain vs. frequency and phase vs. frequency analysis methods. From the comparison, the proposed technique is found to be superior over the gain technique in detection and localization of faults. Finally, a method for identification and localization of faults by clustering is exhibited, which utilizes our proposed technique for better performance.

Performance Evaluation of 32-nm CNT-OPAMPs in Analog Circuits: Design and Comparison of Leapfrog Filters

In this paper, we have presented the design and characteristic performance evaluation of a 6-order Leapfrog Filter. First we designed the filter by using Silicon-based CMOS Operational Amplifiers (Si-OPAMPs). Then we designed the filter with Carbon Nanotube-based Operational Amplifiers (CNT-OPAMPs) using a benchmark nine-transistor Operational Amplifier (OPAMP) model with single-walled Carbon Nanotube Field-Effect Transistors (SW-CNTFETs) as primary building-blocks for 32nm technology. We compared the performance between the two and achieved higher phase margin, improved power dissipation, and significantly higher input resistance for the CNT-OPAMP based filter. Then we further evaluated the performance of the CNT-OPAMP based filter by changing the number of SWNTs used in the intrinsic channel region of the CNTFET, keeping all other design parameters the same. Our simulation-based assessment has shown a satisfactory superiority for CNT-OPAMP filter design in comparison with Si-based CMOS filter design. The results obtained suggest that the CNT-OPAMP has a promising potential for low-power, high-speed applications in both analog and mixed-signal nanoelectronic circuits.

Performance evaluation of a 32-nm CNT-OPAMP in analog circuits: Design and comparison of Elliptical filters

In this paper, we have presented the design and characteristic performance evaluation of an Elliptical filter for 800 Hertz bandwidth. First we designed the filter by using Silicon-based CMOS Operational Amplifiers (Si-OPAMPs). Then we designed the filter with Carbon Nanotube-based Operational Amplifiers (CNT-OPAMPs) using a benchmark nine-transistor Operational Amplifier (OPAMP) model with single-walled Carbon Nanotube Field-Effect Transistors (SW-CNTFETs) as primary building-blocks for 32nm technology. We compared the performance between the two and achieved higher phase margin, improved power dissipation, and significantly low output resistance for the CNT-OPAMP based filter. Then we further evaluated the performance of the CNT-OPAMP based filter by changing the number of SWNTs used for making each of the CNTFET, keeping all other design parameters the same. Our simulation-based assessment has shown a satisfactory superiority for CNT-OPAMP filter design in comparison with Si-based CMOS filter design. The results obtained suggest that the CNT-OPAMP has a promising potential for low-power, highspeed applications in both analog and mixed-signal nanoelectronic circuits.

Analysis of propagation model performance in WiMAX (IEEE 802.16e)-based wireless mobile vehicular networks

WiMAX is an appropriate wireless technology for networked vehicular applications in intelligent transportation system because of its mobility support at vehicular speeds and its inherent wide coverage. In this paper, performance of a WiMAX (IEEE 802.16e Standard) mobile vehicular network is investigated under different existing empirical propagation models, hand-off scenarios and variation of speed for a moving MS. The study leads to the selection of a suitable propagation model for better performance with higher throughput and lower path loss. The network simulation is done by NCTUns simulation tool with design paradigms specified for WiMAX (IEEE 802.16e).

Design and Performance Evaluation of a 10GHz 32nm-CNTFET IR-UWB Transmitter for Inter-Chip Wireless Communication

In this paper, we have presented the design and performance evaluation of a 10GHz 32nm-CNTFET IR-UWB transmitter for inter-chip wireless transmission. We have designed the transmitter using a VCO-based high speed clock generator and a positive and a negative monocycle Gaussian pulse generator. RF compatible Carbon Nano-Tube Field Effect Transistors (CNTFETs) have been used as the building blocks of the oscillator and the logic gates. The final design has resulted to a 7-channel-SWNT CNTFET-based transmitter for optimum 10GHz data rate with a promising 650mV pulse amplitude and only 1.069mW power consumption with a -32.27dB output. This transmitter can also operate satisfactorily upto 15GHz. The results show promising superiority over existing transmitters regarding high data rate, low power loss and high pulse amplitude.

Self-consistent determination of threshold voltage of In-rich Gate-All-Around In x Ga 1−x As nanowire transistor incorporating quantum mechanical effect

This paper presents quantum definition based threshold voltage calculation of Gate-All-Around InGaAs nanowire transistor. Though similar determination was previously established for TG FinFETs in recent literature, application of this method on Gate-All-Around Nanowire Transistor is yet to be done. A self-consistent solver, which takes wave function penetration and other quantum mechanical effects into account, has been used here to establish the capacitance-voltage characteristics that have been used for threshold voltage calculation. Using the extracted threshold voltages, effect of channel width and channel material composition variation on threshold has been studied and a modification of classical analytical formula is proposed based on a fitting parameter.

Analytical modeling of gate capacitance and drain current of gate-all-around In x Ga 1−x As nanowire MOSFET

Gate-all-around structure with III-V channel material shows improved channel performance with high carrier mobility and less short channel effect and therefore is being studied rigorously for next generation transistors. We propose an analytical model to calculate gate capacitance and drain current of gate-all-around (GAA) nanowire MOSFET, a prospective device to replace the state-of-art FinFET in near future as per ITRS roadmap. The gate capacitance in strong inversion region is modeled incorporating quantum mechanical effects which are verified against the results obtained from self-consistent simulation of Schrödinger-Poisson equation appeared in recent literature. This model can also be extended for calculating gate capacitance in strong inversion region of different Multi-gate MOSFETs. A Spice compatible analytic model for drain current is also proposed which shows excellent agreement with the reported results of experimentally demonstrated In0.53Ga0.47As (2×1016/cm3) GAA MOSFET. Using the proposed formula for gate capacitance in strong inversion region and drain current together with semi-numerical ballistic MOSFET model, the performance of In0.53Ga0.47As (2×1016/cm3) GAA MOSFET is examined. This device is found suitable for ultra-high performance application with very high intrinsic cut-off frequency resulting from very low gate delay and very high on current and gate capacitance. The proposed analytical model of gate capacitance utilizes a modified form of co-axial cable capacitance along with the quantum capacitance limit to form a computationally efficient formula that is in well agreement with the results appeared in recent literature. On the other hand, Landauer-Buttiker formula and compact model for drain current of planar bulk-MOSFET are utilized to form the model for analytic drain current that shows excellent agreement with the experimental results appeared in the literature in recent past. The proposed model can be used for Spice modeling and circuit simulation of In0.53Ga0.47As GAA MOSFET. Moreover, this model is flexible and can be modified for other high performance multi-gate nano-devices.

Uncoupled mode space approach towards transport modeling of Gate-All-Around In x Ga 1−x As nanowire MOSFET

Since the fabrication of first III-V Gate-All-Around (GAA) MOSFET it is under extensive research, as it is one of the potential candidates to replace the state of art tri-gate FinFETs, to continue progressive scaling. In this work, transport characterization of experimentally demonstrated gate-all-around (GAA) InxGa1-xAs nanowire MOSFET in near-ballistic regime is performed using 3D self-consistent Schrödinger-Poisson solver based on Uncoupled Mode Space approach, taking wave function penetration and other quantum mechanical effects into account. The effects of channel length variation on transport characteristics are also examined.

Ballistic performance limit and gate leakage modeling of Rectangular Gate-all-around InGaAs Nanowire Transistors with ALD Al 2 O 3 as Gate Dielectric

This paper presents the ballisitic current limit and gate leakage due to direct tunneling of a Rectangular Gate-all-around InGaAs Nanowire Transistor and their variation with fin width, oxide thickness and In compostion in InGaAs. Ballistic current is found to be higher (1.5×1011 Am-2) for about 20nm fin width, sub-5nm oxide thickness and In-rich InGaAs channel. On the other hand, gate leakage is prominent for sub-4nm oxide thickness, larger fin width and In-rich InGaAs.

Analytical modeling of potential profile and threshold voltage for rectangular gate-all-around III–V nanowire MOSFETs with ATLAS verification

The 3-D poissons equation with eight boundary conditions is solved analytically and an analytical model of potential profile and threshold voltage for rectangular gate-all-around III-V nanowire MOSFET device is developed with quantum correction. Dependence of threshold voltage on channel width, oxide thickness, gate-length, doping and channel material composition are determined from the developed model with experimental and ATLAS verification.. The model agrees well with experimental and simulation results and offers an insight to the device performance.