Saeed Uz Zaman Khan

Self-consistent determination of threshold voltage of In-rich Gate-All-Around In x Ga 1−x As nanowire transistor incorporating quantum mechanical effect

This paper presents quantum definition based threshold voltage calculation of Gate-All-Around InGaAs nanowire transistor. Though similar determination was previously established for TG FinFETs in recent literature, application of this method on Gate-All-Around Nanowire Transistor is yet to be done. A self-consistent solver, which takes wave function penetration and other quantum mechanical effects into account, has been used here to establish the capacitance-voltage characteristics that have been used for threshold voltage calculation. Using the extracted threshold voltages, effect of channel width and channel material composition variation on threshold has been studied and a modification of classical analytical formula is proposed based on a fitting parameter.

A physically based compact I–V model for monolayer TMDC channel MOSFET and DMFET biosensor

In this work, a compact transport model has been developed for monolayer transition metal dichalcogenide (TMDC) channel MOSFET. The analytical model solves the Poissons equation for the inversion charge density to get the electrostatic potential in the channel. Current is then calculated by solving the drift-diffusion equation. The model makes gradual channel approximation to simplify the solution procedure. The appropriate density of states obtained from the first principle density functional theory simulation has been considered to keep the model physically accurate for monolayer TMDC channel FET. The outcome of the model has been benchmarked against both experimental and numerical quantum simulation results with the help of a few fitting parameters. Using the compact model, detailed output and transfer characteristics of monolayer WSe2 FET have been studied, and various performance parameters have been determined. The study confirms excellent ON and OFF state performances of monolayer WSe2 FET which could be viable for the next generation high-speed, low power applications. Also, the proposed model has been extended to study the operation of a biosensor. A monolayer MoS2 channel based dielectric modulated FET is investigated using the compact model for detection of a biomolecule in a dry environment.

Analytical modeling of gate capacitance and drain current of gate-all-around In x Ga 1−x As nanowire MOSFET

Gate-all-around structure with III-V channel material shows improved channel performance with high carrier mobility and less short channel effect and therefore is being studied rigorously for next generation transistors. We propose an analytical model to calculate gate capacitance and drain current of gate-all-around (GAA) nanowire MOSFET, a prospective device to replace the state-of-art FinFET in near future as per ITRS roadmap. The gate capacitance in strong inversion region is modeled incorporating quantum mechanical effects which are verified against the results obtained from self-consistent simulation of Schrödinger-Poisson equation appeared in recent literature. This model can also be extended for calculating gate capacitance in strong inversion region of different Multi-gate MOSFETs. A Spice compatible analytic model for drain current is also proposed which shows excellent agreement with the reported results of experimentally demonstrated In0.53Ga0.47As (2×1016/cm3) GAA MOSFET. Using the proposed formula for gate capacitance in strong inversion region and drain current together with semi-numerical ballistic MOSFET model, the performance of In0.53Ga0.47As (2×1016/cm3) GAA MOSFET is examined. This device is found suitable for ultra-high performance application with very high intrinsic cut-off frequency resulting from very low gate delay and very high on current and gate capacitance. The proposed analytical model of gate capacitance utilizes a modified form of co-axial cable capacitance along with the quantum capacitance limit to form a computationally efficient formula that is in well agreement with the results appeared in recent literature. On the other hand, Landauer-Buttiker formula and compact model for drain current of planar bulk-MOSFET are utilized to form the model for analytic drain current that shows excellent agreement with the experimental results appeared in the literature in recent past. The proposed model can be used for Spice modeling and circuit simulation of In0.53Ga0.47As GAA MOSFET. Moreover, this model is flexible and can be modified for other high performance multi-gate nano-devices.

Uncoupled mode space approach towards transport modeling of Gate-All-Around In x Ga 1−x As nanowire MOSFET

Since the fabrication of first III-V Gate-All-Around (GAA) MOSFET it is under extensive research, as it is one of the potential candidates to replace the state of art tri-gate FinFETs, to continue progressive scaling. In this work, transport characterization of experimentally demonstrated gate-all-around (GAA) InxGa1-xAs nanowire MOSFET in near-ballistic regime is performed using 3D self-consistent Schrödinger-Poisson solver based on Uncoupled Mode Space approach, taking wave function penetration and other quantum mechanical effects into account. The effects of channel length variation on transport characteristics are also examined.

Effect of temperature on ballistic transport of cylindrical (10, 0) CNTFET

Carbon nanotube (CNT) shows near-ballistic transport and therefore has become a topic of extensive research. Cylindrical CNT field effect transistor (CNTFET) shows better performance than double gate CNTFETs which is simulated here self-consistently using tight-binding approximation exploiting the coaxial symmetry taking intrinsic (10, 0) zigzag nanotube as channel material, doped and gate-overlapped source/drain . The effect of temperature on transport properties is examined in ballistic regime. The analysis reveals that drain current is almost independent of temperature, where the sub-threshold swing decreases significantly with temperature and transconductance falls down at lower temperature for sub-0V gate bias.

Ballistic performance limit and gate leakage modeling of Rectangular Gate-all-around InGaAs Nanowire Transistors with ALD Al 2 O 3 as Gate Dielectric

This paper presents the ballisitic current limit and gate leakage due to direct tunneling of a Rectangular Gate-all-around InGaAs Nanowire Transistor and their variation with fin width, oxide thickness and In compostion in InGaAs. Ballistic current is found to be higher (1.5×1011 Am-2) for about 20nm fin width, sub-5nm oxide thickness and In-rich InGaAs channel. On the other hand, gate leakage is prominent for sub-4nm oxide thickness, larger fin width and In-rich InGaAs.

Analytical modeling of potential profile and threshold voltage for rectangular gate-all-around III–V nanowire MOSFETs with ATLAS verification

The 3-D poissons equation with eight boundary conditions is solved analytically and an analytical model of potential profile and threshold voltage for rectangular gate-all-around III-V nanowire MOSFET device is developed with quantum correction. Dependence of threshold voltage on channel width, oxide thickness, gate-length, doping and channel material composition are determined from the developed model with experimental and ATLAS verification.. The model agrees well with experimental and simulation results and offers an insight to the device performance.

Characterization of interface trap density of In-rich InGaAs Gate-all-around nanowire MOSFETs

This paper presents the characterization of interface trap charge for 30 nm In_0.53Ga_0.47As channel Gate-all-around field effect transistor (GAAFET) using ALD Al₂0₃ as the oxide. The interface trap charge density (D_it) is extracted from CV model through self consistent iterations. The CV model is formulated by self consistent Schrödinger-Poisson solver. Wave function penetration effect has been considered while solving the Schrodinger equation. The result gives an intuition about the D_it profile. The difference between the initial assumed CV and the final CV demonstrates the effect of D_it on the CV profile of the device. We repeated the same for In_.65Ga_.35As and In_.75Ga_.25As and then did a comparative study of the devices. The donor-like traps dominate the D_it profile for higher mole-fraction of In in InGaAs which in our case is In_0.75Ga_0.25As. The stronger inversion of In-rich channels and hence, better transport characteristics is evident from these results.