Quazi D. M. Khosru

Parametrization of a silicon nanowire effective mass model from sp3d5s* orbital basis calculations

We parameterize a silicon nanowire effective mass model to facilitate device simulation, where the mass depends on the wire dimension. Parametrization is performed for n-channel silicon nanowire transistors from sp3d5s* atomic orbital basis tight-binding calculations. The nanowires used in this study are grown in 1 0 0 and 1 1 0 directions. With the parameterized nanowire effective masses, we then calculate the current and compare against the full band I–V. The full band I–V is calculated for 1 1 0 wires of cross sections 0.82 nm × 0.82 nm and 1.2 nm× 1.2 nm due to computational resource limitation. The full-band and effective-mass I–V characteristics of 1.2 nm × 1.2 nm wire show very good agreement. However, a relatively larger mismatch is observed for the 0.82 nm × 0.82 nm wire, especially at the lower gate biases. This is because the current has both the thermal and tunneling components, and the nanowire effective-mass model overestimates the tunneling current. This overestimation is relatively larger for thinner wires. The thermal component of current is the same in both the nanowire effective-mass and full-band models. The performance metrics, namely the intrinsic switching delay and the unity current gain frequency are evaluated from the full-band calculations. The device has a near ideal subthreshold slope, a fraction of picosecond switching delay and a tera Hertz unity current gain frequency.

On the distinction between triple gate (TG) and double gate (DG) SOI FinFETs: A proposal of critical top oxide thickness

Distinction between triple gate (TG) and double gate (DG) silicon-on-insulator (SOI) FinFETs is presented here on the basis of their electrostatic and transport characteristics. A study missing in previous works on DG and TG FinFETs is the characterization of these structures with respect to the variation of top oxide thickness. In fact an exact value of the top-oxide thickness that can differentiate DG FinFETs from TG ones has not been reported yet. From this perspective, electrostatic and transport characteristics of DG and TG FinFETs having sub-10 nm fin dimensions are investigated in this work as a function of the top oxide thickness. To duly incorporate the quantum-mechanical (QM) effects in such nanoscale regime of operation, the devices are simulated by self-consistently solving the coupled Schrödingers and Poissons equations. Simulation results suggest that DG and TG FinFETs can be differentiated by a parameter which we define in our work with respect to the surface potentials existing beneath the top and side gates. This finding in effect proposes a critical top oxide thickness of FinFET that can draw the distinction between its DG and TG variants. The results also indicate that deposition of top oxide layer beyond a limit does not bring about any significant change in the electrostatic and transport characteristic of DG FinFETs in the ballistic limit.

Negative Capacitance Tunnel Field Effect Transistor: A Novel Device With Low Subthreshold Swing and High On Current

In this paper we propose a modified structure of TFET incorporating ferroelectric oxide as the complementary gate dielectric operating in negative capacitance zone, called the Negative Capacitance Tunnel FET (NCTFET). The proposed device effectively combines two different mechanisms of lowering the sub threshold swing (SS) for a transistor garnering a further lowered one compared to conventional TFET. A simple yet accurate analytical tunnel current model for the proposed device is also presented here. The developed analytical model demonstrates high ON current at low

An analytical surface potential model for pocket implanted Sub-100 nm n-MOSFET

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Linear pocket profile based threshold voltage model for Sub-100 nm n-MOSFET incorporating substrate and drain bias effects

and exhibits lower SS.

Effect of gate bias on channel in depletion-all-around operation of the SOI four-gate transistor

This paper presents an analytical surface potential model for pocket implanted sub-100 nm n-MOSFET. The model is derived by solving the Poissonpsilas equation in the depletion region at the surface with the appropriate boundary conditions at source and drain. The model includes the effective doping concentration of the two linear pocket profiles at the source and drain sides of the device. The model also incorporates the drain and substrate bias effect below and above threshold conditions. The simulation results show that the derived surface potential model has a simple compact form that can be utilized to study and characterize the pocket implanted advanced ULSI devices.

Analysis of efficiency optimization for PFM mode switching DC-DC boost regulator

This paper presents a threshold voltage model of pocket implanted sub-100 nm n-MOSFETs incorporating the drain and substrate bias effects using two linear pocket profiles. Two linear equations are used to simulate the pocket profiles along the channel at the surface from the source and drain edges towards the center of the n-MOSFET. Then the effective doping concentration is derived and is used in the threshold voltage equation that is obtained by solving the Poissonpsilas equation in the depletion region at the surface. Simulated threshold voltages for various gate lengths fit well with the experimental data already published in the literature. The result is compared with two other pocket profiles used to derive the threshold voltage models of n-MOSFETs. The comparison shows that the linear model has a simple compact form that can be utilized to study and characterize the pocket implanted advanced ULSI devices.

Self-Consistent Modeling of Ultra Thin Body Double Gate MOSFET

In depletion-all around (DAA) operation of SOI four-gate transistor (G4-FET), the conducting channel can be surrounded by depletion regions induced by independent vertical MOS gates and lateral JFET gates. This enables majority carriers to flow through the volume of the silicon film far from both silicon/oxide and p+ gate/n-channel interfaces. A numerical model using FEMLAB with MATLAB is developed to obtain the potential distribution solving 2-D Poisson equation using finite element method. This model is extendable to fully depleted (FD) structure. Using this model, effect of gate bias on the location and size of the conducting channel is studied. Gradual change of the size of the conducting channel from drain to source is also studied when drain is positively biased. Under appropriate gate bias voltages, the cross-section of the channel may be made sufficiently narrow to invoke quantum mechanical effects.

On the Physically Based Compact Gate

A mathematical analysis of efficiency optimization for PFM (pulse frequency modulation) mode boost regulator has been presented in this paper. Based on the load demand, input voltage and output voltage a PFM mode booster can operate in single pulse or multi pulse operation. The presented analysis reveals a relationship between operating efficiency and mode of operation considering the external and internal parameters for which loss occurs. This paper also presents a relationship between maximum load delivering capacity and inductor size where separate modes of operation are distinguished.

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An accurate and efficient one dimensional self-consistent numerical model of double gate MOS structure is presented based on finite element method. The model is developed using FEMLAB considering wave function penetration effect into gate oxide. Hence, penetration effect is revealed and presented for full depleted double gate MOSFET. Accuracy of the model has been verified by comparing with established results.