Fan-Ta Chen

A 10-Gb/s CML I/O Circuit for Backplane Interconnection in 0.18-

A 10-Gb/s current mode logic (CML) input/output (I/O) circuit for backplane interconnect is fabricated in 0.18-mu m 1P6M CMOS process. Comparing with conventional I/O circuit, this work consists of input equalizer, limiting amplifier with active-load inductive peaking, duty cycle correction and CML output buffer. To enhance circuit bandwidth for 10-GB/s operation, several techniques include active load inductive peaking and active feedback with current buffer in Cherry-Hooper topology. With these techniques, it reduces 30%-65% of the chip area comparing with on-chip inductor peaking method. This design also passes the interoperability test with switch fabric successfully. It provides 600- mVpp differential voltage swing in driving 50-Omega output loads, 40-dB input dynamic range, 40-dB voltage gain, and 8-mV input sensitivity. The total power consumption is only 85 mW in 1.8-V supply and the chip feature die size is 700 mum times 400 mum.

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This paper presents an inductive intrinsic parasitic feedback technique to enhance the circuit bandwidth of the electro-absorption/Mach-Zehnder optical modulator driver with high-voltage swing-driving capability. The modulator consists of a series-shunt inductor peaking predriver stage and a multicascode postdriver stage. The postdriver stage integrates the proposed inductive intrinsic parasitic feedback network, the interstage series inductor-peaking scheme, and the auxiliary source degeneration structure. The chip is fabricated in 0.13- μm mixed-signal 1P8M standard CMOS process with a die size of 900×800 μm2. The operation data rate of this design is measured up to 20-Gb/s with 3.7 VPP S.E. output amplitude swing, driving 50-Ω resistive load with input signal less than 250 mV. The measured rise/fall time of the output electrical eye diagram is less than 20 ps and the total power consumption is 0.9 W with 1.2/4.0 V dual supplies.

m CMOS Technology

This paper presents a rotational phase frequency detector (RPFD) for reference-less clock and data recovery circuit (CDR). The proposed RPFD changes the bang-bang phase detector (BBPD) characteristic from a bidirectional phase detection to an unilateral phase detection for capturing clock frequency. The phase-and-frequency lock loop (PFLL) locks the clock frequency and the clock phase alternatively. The single-loop CDR replaces the dual-loop CDR so as to eliminate the noise contribution from the frequency lock loop (FLL). This proposed design is fabricated in TSMC mixed-signal 1P9M 90-nm standard CMOS process with overall die size of 0.71- mm2. With input 10-Gb/s data of a 231-1 PRBS, the CDR tracks free running clock over the capture range of 1.48 GHz and locks in the acquisition time of 20 μs. At the same time, the peak-to-peak jitters show only 5.0 ps in the recovered clock and exhibits 15.11 ps in the recovered data. The measured chip consumes 92 mW with 1.0-V supply voltage.

20-Gb/s CMOS EA/MZ Modulator Driver With Intrinsic Parasitic Feedback Network

A load-balanced Birkhoff-von Neumann (LB-BvN) 4 × 4 switch fabric IC is proposed for feedback-based switch systems. This is fabricated in 0.13- μm CMOS technology and the chip area is 1.380 × 1.080 mm2. The overall data rate of the LB-BvN 4 × 4 switch fabric IC is up to 32 Gb/s (8 Gb/s/channel) with only 0.8 ns propagation delay. The LB-BvN switch is highly recommended for constructing the next-generation terabit switch. In a feedback-based switch system, the long propagation delay of the switch module reduces the system throughput significantly. In this paper, we present a scalable LB-BvN 4 × 4 switch fabric IC directly in the high-speed domain. By observing the deterministic switching pattern of the N×N LB-BvN switch, we present a low-complexity pattern generator that reduces the PG complexity from O(N3) to O(1). This technique reduces the propagation delay of the switch module from 30 to 0.8 ns, and also provides 80% area saving and 85% power saving compared to serializer-deserializer interfaces. The proposed LB-BvN 4 × 4 switch fabric IC is suitable for feedback-based switch systems to solve the throughput degradation problem.

A 10-Gb/s Low Jitter Single-Loop Clock and Data Recovery Circuit With Rotational Phase Frequency Detector

In this paper, we present a 7 Gbps/Ch quad SerDes integrated with a 4times4 load-balanced switch fabric circuit for high speed networking applications. To achieve high-speed and low area, we propose an area-saving RF model device for the SerDes design. The area-saving RF model has almost the same speed and jitter performance with the RF model but only consumes one half of the area. In our hybrid design of the SerDes architecture, the area-saving RF model mixed with the baseband model can reduce 75% of area compared with the design using only the conventional RF model. The grounded coplanar waveguide (GCPW) type transmission line is also employed to reduce the clock tree skew for the quad SerDes to within 1 ps. The total area is 3 mm times 2.48 mm, including the switch fabric, the quad SerDes interface, and a LC-PLL. In our results, each input/output port of the 4x4 switch fabric can achieve 7 Gbps data rate, and the overall throughout is 28 Gbps.

Low Propagation Delay Load-Balanced 4

This paper explores the use of transformer-coupled (TC) technique for the 2:1 MUX and the 1:2 DEMUX to serialize-and-deserialize (SerDes) high-speed data sequence. The widely used current-mode logic (CML) designs of latch and multiplexer/demultiplexer (MUX/DEMUX) are replaced by the proposed TC approach to allow the more headroom and to lower the power consumption. Through the stacked transformer, the input clock pulls down the differential source voltage of the TC latch and the TC multiplexer core while alternating between the two-phase operations. With the enhanced drain-source voltage, the TC design attracts more drain current with less width-to-length ratio of NMOS than that of the CML counterpart. The source-offset voltage is decreased so that the supply voltage can be reduced. The lower supply voltage improves the power consumption and facilitates the integration with low voltage supply SerDes interface. The MUX and the DEMUX chips are fabricated in 65-nm standard CMOS process and operate at 0.7-V supply voltage. The chips are measured up to 40-Gb/s with sub-hundred milliwatts power consumption.

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In the paper, a novel 2.56/3.2Gb/s full-rate phase detector is developed for integration with Clock Data Recovery (CDR) circuit in high speed SerDes applications. An Extended Phase Detector (EPD) circuit is proposed to replace the full-rate Hogge architecture. To incorporate a LC-tank voltage control oscillator with cross-coupled pair and a differential charge pump with common mode feedback. The Digitally Assisted Lock Detector (DALD) circuitry provides a timing decision for switching dual loops between phase or frequency detector in the CDR circuits. The CDR circuit is fabricated in a 0.18 ·m 1P6M Standard CMOS process in an area of 0.8µ1.0 mm2. This CDR chip exhibits a low jitter performance of 2.12 ps RMS in the recovered clock and a BER is 3.5 × 10−9 with PRBS of 231-1 sequence. The power consumption is 136mW with a 1.8V supply at 3.2Gb/s.

4 Switch Fabric IC in 0.13-

This paper presents an injection-locking clock and data recovery circuit (CDR) for serial link receivers. A transformer-coupled injection-locking scheme with all passive components is proposed to lock the quadrature voltage controlled oscillator (QVCO) to align the received data. The quad-rate CDR successfully regenerates the serial 100 Gb/s PRBS 231-1 data into 4 parallel data streams at 25 Gb/s. The fabricated chip occupies 1.92 mm2 in 65 nm standard CMOS process with recovered data peak-to-peak jitter of 0.84ps and consumes 130 mW power with 1.0-V supply.

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In this paper, a low propagation delay, low power, and area-efficient 4×4 load-balanced switch circuit for feedback-based system is presented. In this periodic and deterministic switch, only two DFFs are used to implement a pattern generator which is a O(N3) hardware complexity in traditional matching algorithm based N×N switch. For packet reordering, a feedback path is established in series of symmetric patterns. As comparing with commercial switch systems, we implement a 4×4 switch IC directly in high speed domain without the use of SERDES interfaces to achieve low propagation delay and high scalability. In CML output buffer, PMOS active load and active back-end termination are introduced. A stacked current source and symmetric topology in CML-DFF are adopted. From our results, this work efficiently deducted 28ns propagation delay, 80% area and 80% power introduced by the SERDES interface. The throughput rate is up to 32Gbps (8Gbps/Ch).