Jen-Ming Wu

Reconfigurable FFT Design for Low Power OFDM Communication Systems

The FFT processor is the most speed critical part in the multi-carrier orthogonal frequency division multiplexing (OFDM) communication system. In these systems, low power is usually one of the major concerns. We propose a memory based recursive FFT design in FPGA for the low power base-band OFDM transmitter and receiver for WiMax (wireless metropolitan area network) application. It is implemented by radix-8 FFT. As results, the power consumption will be reduced by 28% compared to radix-4 FFT. The proposed architecture has three advantages: (1) fewer butterfly iterations to reduce power consumption, (2) pipeline of radix-8 butterfly to speed up clock frequency, (3) even distribution of memory access to make the best utilization efficiency of SRAM ports

MIMO Active Interference Alignment for Underlay Cognitive Radio

In this paper, we present a novel scheme that aligns the interference from the antennas of the cognitive user (CU) such that the interference to the primary user (PU) is nullified or minimized. The two-user multiple-input multiple-output (MIMO) interference channel is considered. We assume that the transmission bandwidth of the CU is wider than that of the PU, and the spectrum of the PU is called victim band. Because of the unequal transmission bandwidth, the sampling rates of the two users are not necessarily equal. Two sources of interferences are considered in the alignment. One source is the spatial interference from different antennas of the CU. The other source is the intercarrier interference (ICI) from the un-victim band of CU to the victim band of PU. An active antenna of the cognitive user is used to align with the spatial interference from the other antennas of the cognitive user and ICI such that the interference to the PU is nullified. The simulation shows that the scheme creates a greater than -200dB notch on the transmission spectrum of the victim band. This scheme allows the CU to utilize the victim band simultaneously with the PU and leads to underlay cognitive radio transmission. We also present a successive interference cancellation scheme at the cognitive receiver to detect the signal within the victim band. The error performance at the cognitive receiver of this underlay cognitive radio system is presented as well.

Iterative Interference Cancellation for STBC-OFDM Systems in Fast Fading Channels

The performance of a space-time block coded orthogonal frequency-division multiplexing (STBC-OFDM) system often relies on the assumption of quasi-static channels. For the time-varying multipath channel, co-channel interference (CCI) and inter-carrier interference (ICI) occur and performance degrades seriously. In this paper, we propose an iterative interference cancellation scheme to reduce both CCI and ICI jointly. In particular, a list successive interference cancellation (List-SIC) algorithm is presented to obtain a candidate list to obtain soft information used in the CCI cancellation. Furthermore, an ICI cancellation algorithm that uses prior List-SIC information from the preceding iteration is proposed. The simulation results show that the proposed scheme achieves near maximum likelihood (ML) error performance within only two or three iterations in fast fading channels.

A 10-Gb/s CML I/O Circuit for Backplane Interconnection in 0.18-

A 10-Gb/s current mode logic (CML) input/output (I/O) circuit for backplane interconnect is fabricated in 0.18-mu m 1P6M CMOS process. Comparing with conventional I/O circuit, this work consists of input equalizer, limiting amplifier with active-load inductive peaking, duty cycle correction and CML output buffer. To enhance circuit bandwidth for 10-GB/s operation, several techniques include active load inductive peaking and active feedback with current buffer in Cherry-Hooper topology. With these techniques, it reduces 30%-65% of the chip area comparing with on-chip inductor peaking method. This design also passes the interoperability test with switch fabric successfully. It provides 600- mVpp differential voltage swing in driving 50-Omega output loads, 40-dB input dynamic range, 40-dB voltage gain, and 8-mV input sensitivity. The total power consumption is only 85 mW in 1.8-V supply and the chip feature die size is 700 mum times 400 mum.

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This paper presents an inductive intrinsic parasitic feedback technique to enhance the circuit bandwidth of the electro-absorption/Mach-Zehnder optical modulator driver with high-voltage swing-driving capability. The modulator consists of a series-shunt inductor peaking predriver stage and a multicascode postdriver stage. The postdriver stage integrates the proposed inductive intrinsic parasitic feedback network, the interstage series inductor-peaking scheme, and the auxiliary source degeneration structure. The chip is fabricated in 0.13- μm mixed-signal 1P8M standard CMOS process with a die size of 900×800 μm2. The operation data rate of this design is measured up to 20-Gb/s with 3.7 VPP S.E. output amplitude swing, driving 50-Ω resistive load with input signal less than 250 mV. The measured rise/fall time of the output electrical eye diagram is less than 20 ps and the total power consumption is 0.9 W with 1.2/4.0 V dual supplies.

m CMOS Technology

Intelligent environments significantly impact human daily lives through embedded sensing and actuating systems. Wireless sensors that can provide non-contact radio information are indispensable. Impulse radar is positioned as a favorable candidate in monitoring and sensing objects [1-3]. The impulse radio is inherently multipath immune and suitable for precision ranging. Accurately detecting signals with low power impulse radios imposes design challenges to impulse radar receivers. In this work, a direct-sampling receiver is proposed and implemented for an impulse radar system. It can support GHz instantaneous bandwidth and more than 100GS/sec equivalent sampling rate through the high-speed sampling circuits and on-chip timing circuitry. The wide bandwidth scattering time-domain waveforms in the radio interaction between the object and radar can be sampled and digitized by the receiver. It achieves precise measurement of time of arrival (TOA) in a radar system and expands the scalability towards antenna arrays for detection of direction of arrival (DOA) [4].

20-Gb/s CMOS EA/MZ Modulator Driver With Intrinsic Parasitic Feedback Network

In this paper, a novel multiplexer-flip-flop (MUX-FF) topology using the current mode logic (CML) is presented. A CML multiplexer-latch (MUX-latch) is proposed by combining a multiplexer and the loopback storage part of a latch into a single module so that the buffer part of a latch can be removed. A MUX-FF is implemented by cascading two stages of MUX-latches. The output of a MUX-FF is edge-triggered, so it is insensitive to input noise. All the paths from inputs to the output are symmetric. Power and area can be reduced due to the removal of DFFs. Simulation results show that a MUX-FF can achieve a similar frequency as a conventional tree-type MUX by saving 56 % of area and 72 % of power consumption.

A scalable direct-sampling broadband radar receiver supporting simultaneous digital multibeam array in 65nm CMOS

This paper proposes multiplexer-flip-flops (MUX-FFs) to be a high-throughput and low-cost solution for serial link transmitters. We also propose multiplexer-latches (MUX-Latches) that possess the logic function of combinational circuits and storing capacity of sequential circuits. Adopting the pipeline with MUX-FFs, which are composed of cascaded latches and MUX-Latches, many latch gates for sequencing can be removed. Analysis and simulation results show that an 8-to-1 serializer in the pipeline topology with MUX-FFs reduces 52% gate-count compared to that in the traditional pipeline topology. To verify the functions of the proposed design, two chips are implemented with the proposed 4-to-1 MUX-FF and 8-to-1 serializer with MUX-FFs in 90 nm CMOS technology. The measured results show that the MUX-FF and the proposed serializer with MUX-FFs are almost bit-error-free (with BER <; 10-12 ), operating at up to 6 Gbits/s and 12 Gbit/s, respectively.

A novel MUX-FF circuit for low power and high speed serial link interfaces

A UWB impulse radio (IR) timed-array radar using time-shifted direct-sampling architecture is presented. The transmitter array can generate and send a variety of 10GS/s pulses towards targets. The receiver array samples the reflected signal in RF domain directly by time interleaved sampling with equivalent sampling rate of 20 GS/s. The radar system can determine time of arrival (TOA) and direction of arrival (DOA) through time-shifted sampling edges which are generated by on-chip digital-to-time converters (DTC). The proposed architecture has range and azimuth resolution of 0.75 cm and 3 degree respectively. This prototype is implemented in a 0.18μm CMOS technology.

A Novel Low Gate-Count Pipeline Topology With Multiplexer-Flip-Flops for Serial Link

In this paper, we present a modified coefficient ordering based pipelined 256-point FFT/IFFT processor with minimum switching activity for IEEE 802.16-2004 (or WiMAX) system. The fixed radix-4 and single-path pipelined architecture is used in this FFT design. The pipelined architecture provides higher throughput rate comparing with the iterative architecture. We have shown that the low power issue is addressed by minimizing the switching activity using minimum Hamming distance transition. The switching activity of twiddle computation is thus reduced from 181 to 71, i.e. 61% reduction. We have implemented the VLSI design of the OFDM transmitter with 16-bit word length. The signal to quantization noise ratio is improved to 120 dB