Farah Fahim

An on-chip charge cluster reconstruction technique in the miniVIPIC pixel readout chip for X-ray counting and timing

An on-chip algorithm for the allocation of a hit to a single pixel in the presence of charge sharing in a highly segmented pixel detector is presented. It has been developed to advance pixel detector technology for experiments with X-ray beams at a synchrotron facility. Its key elements are: activation of groups of pixels (neighborhood_active), comparisons of peak amplitudes within the active neighborhood, virtual pixels that recover composite signals, ability to create event driven strobes to control comparisons of fractional signals between neighboring pixels and finally latching of the results of these comparisons. The miniVIPIC prototype was designed in a 130 nm process, as a proof of feasibility. The chip contains an array of 32×32 100×100 μm2 pixels. Analog and digital signals are exchanged between pixels, forming an extensive inter-pixel connection grid, whose routing to minimize parasistics, represented the major challenge. The design details of the chip are provided.

Monolithic Active Pixel Matrix with Binary Counters ASIC with nested wells

Monolithic Active Matrix with Binary Counters (MAMBO) V ASIC has been designed for detecting and measuring low energy X-rays. A nested well structure with a buried n-well (BNW) and a deeper buried p-well (BPW) is used to electrically isolate the detector from the electronics. BNW acts as an AC ground to electrical signals and behaves as a shield. BPW allows for a homogenous electric field in the entire detector volume. The ASIC consists of a matrix of 50 × 52 pixels, each of 105x105μm2. Each pixel contains analog functionality accomplished by a charge preamplifier, CR-RC2 shaper and a baseline restorer. It also contains a window comparator with Upper and Lower thresholds which can be individually trimmed by 4 bit DACs to remove systematic offsets. The hits are registered by a 12 bit counter which is reconfigured as a shift register to serially output the data from the entire ASIC.

Radiation tolerance of 65 nm CMOS transistors

We report on the effects of ionizing radiation on 65 nm CMOS transistors held at approximately −20 °C during irradiation. The pattern of damage observed after a total dose of 1 Grad is similar to damage reported in room temperature exposures, but we observe less damage than was observed at room temperature.

Comparison of allocation algorithms for unambiguous registration of hits in presence of charge sharing in pixel detectors

Charge sharing is the fractional collection of the charge cloud generated in a detector by two or more adjacent pixels. It may lead to excessive or inefficient registration of hits comparing to the number of impinging photons depending on how discrimination thresholds are set in typical photon counting pixel detector. The problems are particularly exposed for fine pixel sizes and/or for thick planar detectors. Presence of charge sharing is one of the limiting factors that discourages decreasing sizes of pixels in photon counting mode X-ray radiation imaging systems. Currently, a few different approaches tackling with the charge sharing problem exist (e.g. Medipix3RX, PIXIE, miniVIPIC or PIX45). The general idea is, first, to reconstruct the entire signal from adjacent pixels and, secondly, to allocate the hit to a single pixel. This paper focuses on the latter part of the process, i.e. on a comparison of how different hit allocation algorithms affect the spatial accuracy and false registration vs. missed hit probability. Different hit allocation algorithms were simulated, including standard photon counting (no full signal reconstruction) and the C8P1 algorithm. Also, a novel approach, based on a detection of patterns, with significantly limited analog signal processing, was proposed and characterized.

An Algorithm of an X-ray Hit Allocation to a Single Pixel in a Cluster and Its Test-Circuit Implementation

An on-chip implementable algorithm for allocation of an X-ray photon imprint, called a hit, to a single pixel in the presence of charge sharing in a highly segmented pixel detector is described. Its proof-of-principle implementation is also given supported by the results of tests using a highly collimated X-ray photon beam from a synchrotron source. The algorithm handles asynchronous arrivals of X-ray photons. Activation of groups of pixels, comparisons of peak amplitudes of pulses within an active neighborhood and finally latching of the results of these comparisons constitute the three procedural steps of the algorithm. A grouping of pixels to one <italic>virtual pixel</italic>, that recovers composite signals and event driven strobes, to control comparisons of fractional signals between neighboring pixels are the actuators of the algorithm. The circuitry necessary to implement the algorithm requires an extensive inter-pixel connection grid of analog and digital signals, that are exchanged between pixels. A test-circuit implementation of the algorithm was achieved with a small array of <inline-formula> <tex-math notation=LaTeX>

FASPAX: A fast, integrating detector for the APS-upgrade

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Optimizing floating guard ring designs for FASPAX N-in-P silicon sensors

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A 65 nm CMOS analog processor with zero dead time for future pixel detectors

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