P. Grybos

What does the eye tell the brain?: Development of a system for the large-scale recording of retinal output activity

A multielectrode array system has been developed to study how the retina processes and encodes visual images. This system can simultaneously record the extracellular electrical activity from hundreds of retinal output neurons as a dynamic visual image is focused on the input neurons. The retinal output signals detected can be correlated with the visual input to study the neural code used by the eye to send information about the visual world to the brain. The system consists of the following components: (1) a 32 /spl times/ 16 rectangular array of 512 planar microelectrodes with a sensitive area of 1.7 square mm. The electrode spacing is 60 microns and the electrode diameter is 5 microns. (Hexagonal arrays with 519 electrodes are under development); (2) eight 64-channel custom-designed integrated circuits to platinize the electrodes and AC couple the signals; (3) eight 64-channel integrated circuits to amplify, band-pass filter and analog multiplex the signals; (4) a data acquisition system; and (5) data processing software. This paper will describe the design of the system, the experimental and data analysis techniques, and some first results with live retina. The system is based on techniques and expertise acquired in the development of silicon microstrip detectors for high energy physics experiments.

Pole-Zero Cancellation Circuit With Pulse Pile-Up Tracking System for Low Noise Charge-Sensitive Amplifiers

Modern X-ray imaging systems require low noise high-count-rate multichannel front-end electronics. Such systems widely use charge-sensitive amplifiers (CSA) with pole-zero cancellation (PZC) circuits for sensor readout. CSAs in multichannel ASICs often include continuous reset systems based on MOS transistors discharging the integrating capacitance. Noise requirements for such front-end electronics put the effective CSA feedback resistance in the range of hundreds of MOmega. On the other hand, the high input pulse rate generates a dc voltage shift at the CSA output that modifies the CSA feedback resistance and degrades the PZC circuit performance. In the paper we analyze these problems and propose a novel circuit solution to bias transistors in the CSA feedback and in the PZC circuit. This bias circuit tracks the above mentioned voltage shift at the CSA output and ensures proper cancellation of the CSA feedback pole even in the case of high rates of input pulses. We present measurements of a test structure for the continuous CSA feedback discharge and implementation of this circuit in a fast multichannel ASIC manufactured in the 0.35 mum CMOS technology. The circuit performance for the high input pulse rate is described in detail.

Radiation tolerance of single-sided silicon microstrips

Abstract The RD20 collaboration is investigating the design and operation of an LHC inner tracking detector based on silicon microstrips. Measurements have been made on prototype detectors after irradiation with electrons, neutrons, photons, and protons for doses up to 5 Mrad and fluences up to 10 15 particles/cm 2 . The annealing of effective doping changes caused by high neutron fluences, one of the major limits to detector lifetime at the LHC, is shown to be strongly inhibited by cooling below room temperature. Detailed results are presented on the critical issue of microstrip capacitance. We have also investigated bulk damage caused by high-energy protons, interstrip isolation after neutron irradiation, and MOS capacitors irradiated with electrons and photons.

Energy Efficient Low-Noise Multichannel Neural Amplifier in Submicron CMOS Process

This paper presents a low noise low power neural recording amplifier that occupies a very small silicon area and is suitable to integrate with multielectrode arrays in cortical implants. We analyze main problems in neural recording systems processed in modern submicron technologies, i.e., leakage currents, ability to obtain very large and precisely controlled MOS based resistances and spread of the main system parameters from channel to channel. We also introduce methods allowing to mitigate them. Finally, we present methods allowing to calculate optimal channel dimensions of the recording channels input transistors in order to obtain the lowest Input Referred Noise (IRN) for given power and area requirements. The proposed methodology has been applied in the 8-channel integrated recording ASIC dedicated to the broad range of neurobiology experiments. Each of the recording channels is equipped with the control register that enables to set main channel parameters independently. Thanks to this functionality, the user is capable of setting lower cut-off frequency within the range of 300 mHz-900 Hz. The upper cut-off frequency can be switched either to 30 Hz-290 Hz or 9 kHz, while the voltage gain can be set either to 260 V/V or 1000 V/V. A single recording channel is supplied with 1.8 V and consumes only 11 μW of power, while its input referred noise is equal to 4.4 μV resulting in NEF equal to 4.1.

Noise Optimization of Charge Amplifiers With MOS Input Transistors Operating in Moderate Inversion Region for Short Peaking Times

The noise of a fast charge sensitive amplifier (CSA) with an input MOS transistor operating in the moderate inversion region is discussed. The MOS transistor operation in the moderate inversion region becomes especially important in multichannel readout systems where limited power dissipation is required. The ENC of a CSA followed by a fast shaper is usually dominated by the voltage noise of the input MOS transistor. We carried out noise minimization for such a CSA, searching for an optimum input transistor width. The analyses were made using a simplified EKV model and were compared to HSPICE simulations using a BSIM3v3 model. We considered several CMOS technology generations with minimum transistor gate length ranging from 0.13 mum to 0.8 mum. We studied the sensitivity of ENC to the input transistor width, and propose a simple formula to estimate the optimum transistor width, which is valid in a wide current density range.

A Prototype Pixel Readout IC for High Count Rate X-Ray Imaging Systems in 90 nm CMOS Technology

We report on the design of a prototype IC called PX90 dedicated for readout of hybrid semiconductor detectors used for X-ray imaging applications. The PX90 has dimensions of 4 mm × 4 mm and was designed in CMOS 90 nm technology with 9 metal layers. The core of the IC is a matrix of 40 × 32 pixels with 100 m × 100 m pixel size. A 60 m × 60 m square passivation opening in each pixel allows connecting PX90 to a semiconductor detector using stud bump bonding technique. Each pixel contains two charge sensitive amplifiers with Krummenacher feedback scheme, two second stage amplifiers, two discriminators and two 16-bit ripple counters. The stages are DC-coupled and the front-end electronics uses a fully differential readout scheme. To minimize the effective threshold spread at the discriminators inputs, one 8-bit and one 7-bit trim DACs are used. The PX90 can operate in continuous readout mode and in readout mode separate from exposure. The readout of each pixel has some additional functionality, like compression mode or readout of only given number of bits from each pixel. The data are read out via a single LVDS output with 200 Mbps rate.

Large-scale imaging of retinal output activity

Abstract A system is being developed to study how the retina processes, encodes and communicates information about the visual world to the brain. It will image the activity of retinal output neurons over a region of live retina approaching that used for significant neural computation in the visual cortex. A prototype system consisting of 61 microelectrodes, covering an area of 0.17 mm 2 , is described, including some first results with monkey retina. The plans and status for a system with 512 microelectrodes, covering an area of 1.7 mm 2 , are also given.

Measurements of Matching and High Count Rate Performance of Multichannel ASIC for Digital X-Ray Imaging Systems

We present the measurements of matching and high count rate performance of a 64 channel readout ASIC called DEDIX for high count rate position-sensitive measurements using semiconductor detectors. The ASIC is designed in 0.35 mum CMOS process and its total area is 3900 times 5000 mum2. The DEDIX has a binary readout architecture. Each channel is built of a charge sensitive amplifier (CSA) with a pole-zero cancellation circuit, a shaper, two independent discriminators and two independent 20-bit counters. The size of the input device in CSA has been optimized for a detector capacitance in the range of 1-3 pF per strip. An equivalent noise charge of 110 el rms has been achieved for a total detector capacitance of 1 pF at the shaper peaking time of 160 ns. Internal correction DAC implemented in each channel independently ensures a low spread of discriminator effective threshold, namely 0.4 mV at one sigma level. The mean gain in the multichannel ASIC is 54 muV/el, with a good uniformity from channel-to-channel (sd/mean ap 0.8%). Low noise performance and high rate capability have been demonstrated by the measurement up to and above 1 MHz average rate of input signals.

FPDR90—A Low Noise, Fast Pixel Readout Chip in 90 nm CMOS Technology

We report on the design of a prototype IC called FPDR90 dedicated for readout of hybrid pixel semiconductor detectors used for X-ray imaging applications. The FPDR90 has dimensions of 4 mm × 4 mm and was designed in CMOS 90 nm technology with 9 metal layers. The core of the IC is a matrix of 40 × 32 pixels with 100 μm × 100 μm pixel size. A 50 μm diameter circular passivation opening in each pixel allows connecting FPDR90 to a semiconductor detector using bump bonding technique. Each pixel contains a charge sensitive amplifier (CSA), a main amplifier stage, two discriminators and two 16-bit ripple counters. To minimize the effective threshold spread at the discriminators inputs, one 7-bit and one 6-bit trim DACs are used in each pixel for threshold low and threshold high respectively. The data are read out via a single LVDS output with 200 Mbps rate. Each pixel contains about 1800 transistors and has a nominal power consumption of 42 μW for nominal bias condition. The effective peaking time at the discriminator input is 28 ns and it is mainly determined by the time constants of the CSA. The gain is equal to 32 μV/e- or 64 μV/e- in the low and the high gain mode respectively. In the high gain mode the ENC without the detector is 91 e- rms and rises to 106 e- rms with stud bump-bonded pixel detector. The effective threshold spread at the discriminator input is only 0.76 mV (at one sigma level, with 7-bit trim DACs enabled), which corresponds to 12 e- rms at the input. The maximum count rate per pixel depends on the effective CSA feedback resistance. A dead time in the front-end can be set as low as 117 ns (paralyzable model). The FPDR90 can operate with two energy thresholds in the readout mode separate from exposure. Continuous readout is possible when only one threshold is used.

Radiation damage studies of field plate and p-stop n-side silicon microstrip detectors

Abstract We present results from studies of the properties of dedicated n-side microstrip structures before and after irradiation, with photons to 7 Mrad and fast neutrons to 8 × 10 13 ncm −2 . Both p-stop and field plate devices were investigated, each having a range of strip geometries in order to determine optimal configurations for long-term viability and performance.