Farzaneh Yahyaei-Moayyed

Chip-package-board co-design of a 45nm 8-core enterprise Xeon processor

This work describes the steps in designing the highperformance package for the Nehalem-EX microprocessor, a 45 nm 8-core Intel® Xeon® server product [1]. Nehalem-EX is a complex processor for the expandable/scalable server market which includes 8 cores, 24 MB of cache, 4 point-to-point Quick Path Interconnect (QPI) links, and 4 channels of Scalable Memory Interface (SMI) links — with all links capable of running at 6.4 GT/s. Four separate power supplies, a large die size, power gates for each core, and a 130W thermal design power level all present major packaging challenges. This paper emphasises chip-package-board co-design as being critical to the success of a highperformance package design. A method cost-performance optimization is presented which helps in keeping the package size, layer count and capacitor cost low.

Filter design methodology for low noise power domains in datacenter platforms

This work summarizes key steps for the design of low noise power domains in datacenter and cloud computing platforms using ferrite beads. The methodology described here has been implemented in multiple products including Xeon servers and more specifically in high speed IO power domains that, due to their sensitivity, must have low voltage noise.