Kristopher Frutschy

PREDICTION OF MICROELECTRONIC SUBSTRATE WARPAGE USING HOMOGENIZED THERMOMECHANICAL FINITE ELEMENT MODELS

High-density microelectronic substrates, used in organic CPU packages, are comprised of several polymer, fiber-weave, and copper layers and are filled with a variety of complex features such as traces, micro-vias, Plated-Through-Holes (PTH), and adhesion holes. When subjected to temperature changes, these substrates may warp, driven by the mismatch in Coefficients of Thermal Expansion (CTE) of the constituent materials. This study focused on predicting substrate warpage in an isothermal condition. The numerical approach consisted of three major steps: estimating homogenized (effective) thermomechanical properties of the features; calculating effective properties of discretized layers using the effective properties of the features; and assembling the layers to create 2D Finite Element (FE) plate models and to calculate warpage of the whole substrates. The effective properties of the features were extracted from 3D unit cell FE models, and closed-form approximate expressions were developed using the numerical results, curve fitting, and some simple bounds. The numerical approach was applied to predict warpage of production substrates, analyzed, and validated against experimentally measured stiffness and CTEs. In this paper, the homogenization approach, numerical predictions, and experimental validation are discussed.

Reliability assessment of compression contacts for socketable components

A feasibility study was performed to assess the reliability performance of a CPU packaging technology with a potential new compression socket technology. The feasibility study was based on a newly adopted mechanistic based methodology at Intel, called the use condition methodology, for performing reliability evaluations. In this study, the effects of the electronic package interconnect land gold thickness on the behavior of contact resistances through noncyclic temperature and humidity and fretting motion are detailed. The initial assessment of field use conditions requirements for temperature, humidity, and fretting are described. Mechanical and failure rate modeling results are used to aid in assessing the possible fail mechanisms and to help identify possible solutions for these fail mechanisms. Accelerated testing data was then collected at multiple stress conditions, i.e. bake, temperature and humidity, and highly accelerated stress testing (HAST), to identify acceleration factors for temperature and humidity effects. Fretting evaluations were also performed to assess the performance and to estimate the life of the technology. A risk assessment is given on the feasibility of this type of technology for a specific computing environment using the use condition methodology. Finally, the results of the feasibility assessment are compared and contrasted to the standards based methodology that was used at Intel for CPU package and associated enabling evaluations (where enabling includes items such as sockets and thermal solutions).