Fazida Hanim Hashim

Modelling and Analysis of an Efficient Traffic Network Using Ant Colony Optimization Algorithm

The problem of traffic congestion is a daily occurrence in most major cities and requires an effective solution. New technologies such as the Automotive Navigation System (ANS) in finding the best path for a user helps commuters find their way without getting lost, but it only provides the best path for the user based on the distance factor without considering real traffic situations. The objective of this study is to create an optimum traffic system where traffic congestion can be reduced, besides providing a platform for further research on traffic congestion management. By using the Ant Colony Optimization (ACO) algorithm, the determination of the best path for the user has a higher dependency on the time factor. The simulation was modeled using the JAVA programming language. From the study, the algorithm is shown to improve agent travelling time in the network by between 21.13% and 38.99%.

An automated 3D scanning algorithm using depth cameras for door detection

This paper presents an investigation on the characteristics of Microsoft Kinect depth camera for door detection in an indoor environment. Autonomous vehicles usually have to rely on images when navigating indoors due to network limitations of an indoor environment. Locating a door for exit and entryway is one of the problems that need to be tackled when navigating indoors. In this paper, images from a depth camera are captured and used as a tool for detecting doors. The continuously varied ratios and depth differences in the door images have been analysed. An algorithm for door detection was developed using MATLAB. Experiments using different heights and depths of the Kinect sensor have been performed to verify the efficacy of the algorithm for indoor autonomous flying robots like the quadcopter. The algorithm developed is best performed in a clear path of 3.5 meters. The accuracy of the measurement was influenced by the low resolution of the depth images.

Human activity classification for smart home: A multiagent approach

Smart home research requires study of psychological characteristics of home user. People follow some specific patterns in their life style. Inhabitant activity classification plays a vital role to predict smart home events. The paper proposed a multiagent system to track the user for task isolation. The system is composed of cooperative agents which works by sharing local views of individual agents. An algorithm is derived based on opposite entity state extraction for activity classification. The algorithm clusters the smart home events by isolating opposite status of home appliance. Result shows that the proposed algorithm can successfully identify inhabitant activities of various lengths.

Reliable and cost effective anti-collision technique for RFID UHF tag

This paper presents a proposed Reliable and Cost Effective Anti-collision technique (RCEAT) for Radio Frequency Identification (RFID) Class 0 UHF tag. The RCEAT architecture consists of two main subsystems; PreRCEAT and PostRCEAT. The PreRCEAT subsystem is to detect any error in the incoming messages. Then the identification bit (ID) of the no error packet will be fed to the next subsystem. The PostRCEAT subsystem is to identify the tag by using the proposed Fast-search Lookup Table. The proposed system is designed using Verilog HDL. The system is simulated using Modelsim and synthesized using Xilinix Synthesis Technology. The system has been successfully implemented in hardware using Field Programmable Grid Array (FPGA) Virtex II. The output waveforms from the FPGA have been tested on the Tektronix Logic Analyzer for real time verification. Finally the RCEAT architecture is resynthesized using Application Specific Integrated Circuit (ASIC) technology for on-chip implementation. This technology consists of 0.18 μm Library, Synopsys Compiler and tools. From the hardware verification results, it shows that the proposed RCEAT system enables to identify the tags without error at the maximum operating frequency of 180MHz. The system consumes 7.578 mW powers, occupies 6,041 gates and 0.0375 mm2 area with Data arrival time of 2.31 ns.

Entryway detection algorithm using Kinect's depth camera for UAV application

Small unmanned aerial vehicles (UAVs) are gaining popularity in aiding search and rescue teams in the wake of a disaster. When searching through ruins such as a collapsed building or a building under fire, it is almost impossible for the first rescue team to navigate inside the ruins in search for survivors. Small UAVs such as the quadcopter which is equipped with autonomous capabilities has the potential to navigate through the unknown ruins. One of the basic building blocks for any autonomous vehicle is a fast-detection sensor for detection and avoidance of obstacles. Payload and cost should also be considered when choosing the right sensor. In this study, a feature extraction algorithm using Microsoft Kinect depth camera is presented for application on a quadcopter operating in an indoor environment. The main objective of this project is to develop an algorithm that could detect entryway openings, based on the inputs from a Microsoft Kinect camera that will be mounted on a quadcopter. The algorithm is tested in a T-junction corridor of an office building, with objects such as walls, doors, glass, corridors, and fire extinguisher boxes occupying the space. The algorithm successfully detects all objects by using the depth information of each pixel in relative to other pixels. The ratio of each depth area is calculated to differentiate the entryway from the rest of the objects. The analysis reveals that the accepted ratio for entryway detection is 0.701 with +−5% error while values not within this range are considered as obstacles.

Characterization of DC brushless motor for an efficient multicopter design

The Unmanned Aerial Vehicles (UAV) has recently gained popularity in numerous industries due to its unique capabilities. Multicopters are increasingly replacing conventional helicopters and fixed wing planes as the most commonly manufactured Micro Aerial Vehicles, due to their reasonable price. Unlike the long flight operations of fixed wing planes, multicopters can only be operated for short durations. The performance of multicopter depend on the characteristic of the motor that had being used. Adding further payloads to multicopters will deteriorate the performance in terms of stability and flight time. The objective of this paper is to study the characteristics of brushless direct current motor for the purpose of multicopter design. The experiments to determine the characteristics of brushless direct current motor are divided into two parts. The first part of the experiment is the measurement of lift force, power consumption, and current drain under various loads. The next part of the experiment is the measurement of the propeller RPM. All experiments were conducted using the same propeller, motor and Electronic Speed Controller (ESC) setup. The data collected from the experiments is used to generate five characteristics graphs, which consist of propeller rotation versus throttle, power versus propeller rotation, lift versus throttle, current versus throttle and finally power versus throttle. Besides that, the graph of flight time vs throttle input was estimated. All the data was used to build a reference table to estimate the minimum take-off throttle input and flight time for various multicopter configurations. In conclusion, the reference table and the graphs can be useful in aiding multicopter designers in designing an octocopter.

Low power high-speed current comparator using 130nm CMOS technology

Current comparators are extensively used in current steering (CS) digital to analog data converters (DAC) which are used in almost all digital devices now days. With the growing demand for higher operation speed and longer battery life, it is crucial that the propagation delay and the power consumption of current comparator circuitry be further reduced. To this view in this research, a low power and high-speed CMOS current comparator using a Wilson current mirror circuitry at input stage have been presented. The circuit has been designed using Mentor Graphic — CEDECs Silterra Design Kit based on 0.13 μm standard CMOS process and layout have been presented. The achieved propagation delay of the designed comparator is 0.37ns. The designed circuit consumes 0.3461mW and 0.1915mW power when the difference in input current is ±0.4μA and ±0.1μA respectively. Through performance comparison with converters presented in previous researches, it has been shown that the proposed current converter provides the lowest propagation delay and lowest power consumption for input current difference of ±0.4μA and ±0.1μA. Thus, this research represents a significant improvement of the performance of current comparator circuitry.

Development of an autonomous flight controller circuit with real time data transmission

Controlling a UAV in an emergency situation is a challenging task and it requires a highly skilled person. With modern technologies it is possible to design a UAV which can be controlled by anyone regardless of their skills. The objective of this study is to develop an intelligent quadrotor flight controller for autonomous navigation to aid humans. The intelligent flight controller is realized by adding additional IMU sensors to control more degree of freedoms (DOF) together with real time data communication. The design comprises of electronic circuits for navigation and telemetry developed from scratch with the help of CAD software. An open source flight controller software AeroQuad is used to test the quadrotor dynamics. The sensors data from quadrotor is obtained in real time to study the stability and dynamics of the system. The data collected shows behavior of the quadrotor when hovering and maneuvering.

Design of a low-power high-speed comparator in 0.13μm CMOS

Comparator plays an important role in overall performance of analog to digital converters (ADC) in all modern electronic devices used in handheld to industrial applications. High-speed devices with low voltage and low power are considered essential nowadays. This paper presents a CMOS based comparator design using 0.13 μm CMOS process in Mentor Graphics for ADC applications. The primary goal of this research work is to design high-speed and low power comparator using pre-amplifier latch circuit. The proposed design is powered by 1.2V supply and the output signal exhibits only 0.62ns delay which is very much competitive to the other researches. The comparator dissipates only 1.5nW power which is the lowest reported to date. The proposed design is highly compact occupying only 256 μm2 of silicon space. The proposed circuit will be highly useful for the electronic industries where low-power, high-performance, and compactness of devices are the crucial concerns.

Design and Analysis of CMOS Linear Feedback Shift Registers for Low Power Application

Chip manufacturing technologies have been a key to the growth in all electronics devices over the past decade, bringing added convenience and accessibility through advantages in cost, size, and power consumption. Using recent CMOS technology, LFSR is implemented until layout level which develops low power application. One of the most frequent uses of a LFSR inside a FPGA is as a counter. Using a LFSR instead of a binary counter can increase the clock rate considerably due to the low routing resource required to produce the next state logic. This paper explores the LFSR using different architecture in a 0.18μm CMOS technology. There are 3 type architecture implemented into LFSR which is NAND gates, pass transistor and transmission gates. Those LFSR are compare in term of CMOS layout, hardware implementation and power consumption using Mentor Graphics tools. Thus, it provides analysis of LFSR for low power application in CMOS VLSI.