Noorfazila Kamal

Active inductor based fully integrated CMOS transmit/ receive switch for 2.4 GHz RF transceiver

Modern Radio Frequency (RF) transceivers cannot be imagined without high-performance (Transmit/Receive) T/R switch. Available T/R switches suffer mainly due to the lack of good trade-off among the performance parameters, where high isolation and low insertion loss are very essential. In this study, a T/R switch with high isolation and low insertion loss performance has been designed by using Silterra 0.13µm CMOS process for 2.4GHz ISM band RF transceivers. Transistor aspect ratio optimization, proper gate bias resistance, resistive body floating and active inductor-based parallel resonance techniques have been implemented to achieve better trade-off. The proposed T/R switch exhibits 0.85dB insertion loss and 45.17dB isolation in both transmit and receive modes. Moreover, it shows very competitive values of power handling capability (P1dB) and linearity (IIP3) which are 11.35dBm and 19.60dBm, respectively. Due to avoiding bulky inductor and capacitor, the proposed active inductor-based T/R switch became highly compact occupying only 0.003mm2 of silicon space; which will further trim down the total cost of the transceiver. Therefore, the proposed active inductor-based T/R switch in 0.13µm CMOS process will be highly useful for the electronic industries where low-power, high-performance and compactness of devices are the crucial concerns.

An accurate analytical spur model for an integer-N phase-locked loop

Reference spur is a limiting performance factor in an integer-N phase-locked loop (PLL). In this paper, we investigate the effect of VCO gain, ripple magnitude in VCO tuning voltage and reference frequency with reference spur magnitude. Normally, VCO gain and reference frequency are chosen according to needed system requirement, leaving only the ripple voltage on the VCO control signal to be minimised in order to minimize the reference spur. The ripple voltage is mainly contributed by current mismatch, current leakage, switching delay and discrepancies between the rise and fall times in charge pump circuit. In addition, loop filter is also affecting the ripple voltage. In this paper, we consider these effects analytically to predict ripple voltage in the VCO tuning voltage and hence calculate the reference spur magnitude of the PLL device.

A Phase-Locked Loop reference spur modelling using Simulink

Phase-Locked Loops (PLLs) are a commonly used module in frequency synthesizers as part of RF transceivers. Simulating these modules is very time consuming. Therefore, a number of approaches to evaluate the performance of these modules through high level behavioural modelling are developed, where the focus is on the random noise aspect of these modules. In this paper, we introduce charge pump and Phase/Frequency Detector (PFD) non-idealities in the integer-N PLL behavioural model to estimate the periodic noise, which is also known as reference spurs. In addition, the effect of the VCO gain, loop filter order and loop bandwidth on the reference spurs level are taken into consideration. The proposed model was implemented in Simulink and showed less than ±3% error when compared to transistor level simulations from Cadence Spectre. Using this approach a 10 time improvement in simulation speed was achieved compared to transient analysis from Cadence Spectre.

Design of a low power static frequency divider

Frequency divider is an important unit in phase-locked loop (PLL) which is widely used in RF frequency synthesizer. The divider circuit has been identified as the main contributor to PLL power dissipation. Therefore, frequency divider with low power dissipation is necessary. The objectives of this work are to design a frequency divider with low power dissipation which is able to operate under low supply voltage using Silterra 0.13μm CMOS technology. This work also compares performance of the proposed frequency divider to the conventional frequency divider, which is implemented in MOSFET. The proposed frequency divider is based on TSPC topology. DTMOS and FBB techniques have been adopted in the proposed frequency divider to enable it operate at low supply voltage, results in low power dissipation. The performance of the proposed frequency divider in term of maximum operating frequency, supply voltage, power dissipation and phase noise have been compared to those of conventional frequency divider which is implemented using MOSFET. The result of this work has shown that the proposed DTMOS-FBB frequency divider is able to operate up to 2.5GHz from 0.6V supply voltage. It only dissipates 29μW of power. Compared to the MOSFET frequency divider, at the same operating frequency it dissipates 61 μW from 1.2V supply voltage. It is shown the proposed DTMOS-FBB frequency divider has reduced up to 52% of power dissipation when compared to MOSFET frequency divider.

Low power high-speed current comparator using 130nm CMOS technology

Current comparators are extensively used in current steering (CS) digital to analog data converters (DAC) which are used in almost all digital devices now days. With the growing demand for higher operation speed and longer battery life, it is crucial that the propagation delay and the power consumption of current comparator circuitry be further reduced. To this view in this research, a low power and high-speed CMOS current comparator using a Wilson current mirror circuitry at input stage have been presented. The circuit has been designed using Mentor Graphic — CEDECs Silterra Design Kit based on 0.13 μm standard CMOS process and layout have been presented. The achieved propagation delay of the designed comparator is 0.37ns. The designed circuit consumes 0.3461mW and 0.1915mW power when the difference in input current is ±0.4μA and ±0.1μA respectively. Through performance comparison with converters presented in previous researches, it has been shown that the proposed current converter provides the lowest propagation delay and lowest power consumption for input current difference of ±0.4μA and ±0.1μA. Thus, this research represents a significant improvement of the performance of current comparator circuitry.

Resistorless self-biased curvature compensated sub-1V CMOS bandgap reference

A Bandgap Voltage Reference (BGR) circuit technique for lower voltage supply operation is presented. It eliminates the need of BGR core and resistors by integrating a two-stage cascode operational amplifier (op-amp) biased with a start-up circuitry with all-MOSFET transistors. The circuit is designed in 0.13μm CMOS process technology, produced a 179mV reference voltage at 27°C with 0.4V supply voltage. The simulated voltage reference achieved 0.02ppm/°C temperature coefficient over −60°C to 45°C temperature range as well as ±170mV over supply voltage variation from 0.1V to 1.2V. The design is simulated and verified with Mentor Graphics.

Design and Analysis of CMOS Linear Feedback Shift Registers for Low Power Application

Chip manufacturing technologies have been a key to the growth in all electronics devices over the past decade, bringing added convenience and accessibility through advantages in cost, size, and power consumption. Using recent CMOS technology, LFSR is implemented until layout level which develops low power application. One of the most frequent uses of a LFSR inside a FPGA is as a counter. Using a LFSR instead of a binary counter can increase the clock rate considerably due to the low routing resource required to produce the next state logic. This paper explores the LFSR using different architecture in a 0.18μm CMOS technology. There are 3 type architecture implemented into LFSR which is NAND gates, pass transistor and transmission gates. Those LFSR are compare in term of CMOS layout, hardware implementation and power consumption using Mentor Graphics tools. Thus, it provides analysis of LFSR for low power application in CMOS VLSI.

Dual-mode receiver architecture for Bluetooth and IEEE 802.11b standards

This article presents a dual mode receiver architecture for Bluetooth and IEEE 802.11b standards at 2.4 GHz. In order to fulfill the increasing demand of data capacity, IEEE 802.11 WLAN is one of the most deployed technologies. On the other hand Bluetooth is imperative for wireless personal area network (WPAN) solution. Both standards use the 2.4 GHz band. The architecture specification was based on the optimization of each building block performance for both standards. The overall receiver gain, noise figure (NF) and IIP3 are 29 dB, 3.5 dB and -12.5 dBm which show satisfactory agreement with receiver performance.

Accurate Reference Spur Estimation Using Behavioural Modelling

Reference spur is a periodic noise that can be observed at the output of an integer-N phase-locked loop (PLL). This noise is dominated by circuit non-idealities in phase/frequency detector (PFD) and charge pump. The spur magnitude is linearly related with Voltage Controlled Oscillator (VCO) gain. Estimating this noise using transistor level simulation is time consuming. Therefore, in this paper we present a Simulink behavioural model to accurately estimate the reference spur. PFD delay, charge pump current mismatch, rise and fall times effect and switching delay, in addition to non-linearity in the VCO gain, are all included in this model. The proposed model was used to estimate the reference spur for an 18.5 GHz PLL and the results were compared with transistor level simulation, and show less than 3% difference in the result.

A high-frequency divider in 0.18 µm SiGe BiCMOS technology

High speed frequency dividers are critical parts of frequency synthesisers in wireless systems. These dividers allow the output frequency from a voltage controlled oscillator to be compared with a much lower external reference frequency that is commonly used in these synthesisers. Common trade-offs in high frequency dividers are speed of division, power consumption, real estate area, and output signal dynamic range. In this paper we demonstrate the design of a high frequency, low power divider in 0.18 µm SiGe BiCMOS technology. Three dividers are presented, which are a regenerative divider, a master-slave divider, and a combination of regenerative and master-slave dividers to perform a divide-by-8 chain. The dividers are used as part of a 60 GHz frequency synthesizer. The simulation results are in agreement with measured performance of the regenerative divider. At 48 GHz the divider consumes 18 mW from a 1.8 V supply voltage. The master-slave divider operates up to 36 GHz from a very low supply voltage, 1.8 V. The divide-by-8 operates successfully from 40 GHz to 50 GHz.