J. Andres Torres

Self-aligned double-patterning (SADP) friendly detailed routing

Amongst the possible double patterning strategies for sub 32nm processes, self-aligned double patterning (SADP) has moved from Flash-only processes to more general purpose devices. The reason is that while litho-etch- litho-etc (LELE) process was originally preferred due to its simplicity and relative low cost, its sensitivity to overlay error has prompted the search for other methods. Although the basic SADP process is fairly robust against the overlay error, the robustness of 2D SADP method strongly depends on layout and decomposition styles and decomposability compliance. In this paper, we first discuss different printability challenges for SADP method. Afterward, we propose a SADP-aware detailed routing method, by applying a correct-by-construction approach, to provide SADP-friendly layouts. This method performs detailed routing and layout decomposition concurrently to prevent litho-limited layout configurations. Experimental results show that, compared with a SADP-blind detailed router, the proposed method achieves considerable robustness against lithography imperfection in expense of tolerable wire length overhead.

Challenges and opportunities in applying grapho-epitaxy DSA lithography to metal cut and contact/via applications

Directed self assembly has become a very attractive technology for Fin and contact/via applications. Some of the issues related to pattern placement error, defectivity rates and process integration are actively being addressed by the industry and have not faced significant roadblocks for contact-hole applications. While many DSA applications have been proposed, deploying DSA for Fin structures competes in cost and variability control with SADP techniques. Given the 1D nature of find structures, it is difficult to control fin placement with accuracy better than 4nm 3 sigma. In addition, a second patterning step is needed to remove the un-wanted sections of the grating and leaving behind only the required fin structures, therefore limiting its adoption. On the other hand, DSA applied to contact/via holes has demonstrated low defectivity rates due to improved polymerization and processing techniques, as well as an adequate control to reduce the placement error due to thermal fluctuations during the annealing and cylinder formation process. For that reason, the results from contact/via layers can extend to the metal cut layer printing with DSA grapho-epitaxy. In this paper, we show that DSA provides a promising cost-effective solution for the technology scaling by reducing mask number from N to N-1. It is shown that pxOPC may provide better guiding patterns than the conventional one. In addition, the practical grouping rules for DSA should avoid 2D grouping, avoid putting more than 3 features in a group with different pitches, and avoid grouping features with different sizes. Our recommendations to designers for DSA technology are the following: if the design is to be decomposed with 2 or more DSA masks, then the design rules should be set up in this way: first the minimum pitch is better to be on DSA material’s own natural pitch; second, for each DSA mask, singletons and bar-like grouping shapes with DSA’s natural pitch should be used as much as possible.

Mask assignment and synthesis of DSA-MP hybrid lithography for sub-7nm contacts/vias

Integrating Directed Self Assembly (DSA) and Multiple Patterning (MP) is an attractive option for printing contact and via layers for sub-7nm process nodes. In the DSA-MP hybrid process, an optimized decomposition algorithm is required to perform the MP mask assignment while considering the DSA advantages and limitations. In this paper, we present an optimal Integer Linear Programming (ILP) formulation for the simultaneous DSA grouping and MP decomposition problem for contacts and vias. Then we propose a heuristic and develop an efficient algorithm for solving the same problem. In comparison to the optimal ILP results, the proposed algorithm is 197x faster and results in 16.3% more violations. The proposed algorithm produces 56% fewer violations than the sequential approaches which perform DSA grouping followed by MP decomposition and vice versa.

Self-aligned double patterning (SADP) layout decomposition

Double patterning lithography (DPL) is the most likely manufacturing process for sub-32nm technology nodes; however, there are several double patterning strategies each of which exhibits different layout decomposition challenges. Self-aligned double patterning (SADP) has attracted much interest due to its robustness against overlay errors, but SADP compliance depends strongly on the characteristics of the individual masks generated during the layout decomposition. This work establishes SADP decomposition requirements and proposes a litho-friendly layout decomposition method. First, we explain the main parameters that limit printability of SADP decomposed layouts. In-silico experiments indicate that layout patterns which are printed by the Trim mask may experience the highest levels of image transfer sensitivity. For that reason, these patterns should be assisted by sidewalls of spacer patterns which are robustly printed. Next, we present an ILP-based decomposition method which avoids decomposition conflicts and sensitive Trim edges simultaneously. Our experiments on several industrial designs reveal that the proposed method decreases the total length of sensitive Trim patterns and consequently reduces the overall edge placement error significantly.

ICCAD-2012 CAD contest in fuzzy pattern matching for physical verification and benchmark suite

With the widespread adoption of design for manufacturing techniques and design and process co-optimization as well as the increase in the complexity of the processes to manufacture integrated circuits there is pressing need in finding quickly to calibrate yet accurate and high performing methods to identify layout topologies which may cause yield loss. While full-based simulations provide the most accurate prediction possible their runtime prohibits an adoption at all levels of the design flow. Alternative traditional rule checking including pattern matching techniques are fast but have a limited application in finding locations that were not part the training set. Several approaches to improve the accuracy of the prediction to reduce the number of miss structures and false detections have been proposed, but none have yielded and acceptable tradeoff between accuracy and runtime. This contest is aimed to provide a suite of layouts which highlight the challenges of this application: Widely different classes, limited amount of data and low prediction rates.

Calibration of OPC models for multiple focus conditions

Ability to predict process behavior under defocus has until now relied on explicit calculations, which while accurate, cannot be realistically used in full-chip optical and process correction strategies due to the long run times. In this work, we have applied a vector model for the optics, and a compact model for the resist development process. Simulations with these models are fast enough to be the basis of full-chip OPC. We verify this strategy with an independent set of measurements, and compare it to current lithographic process fitting strategies. The results indicate that by describing optical processes as accurately as possible, the model accuracy improves over a wider range of defocus conditions when compared to the traditional calibration method. As long as the calibration process successfully decouples optical and resist effects, relatively simple resist models deliver excellent accuracy within the noise level of the metrology measurements. Our data are based on one-dimensional and two-dimensional results using a 193nm system using 0.75 NA and off axis illumination with 6% attenuated phase shift mask. In all cases, a wide variety of sub-resolution assist feature rules were used in order to further test the ability of the models to predict various optical and resist environments.

Calibration and application of a DSA Compact model for graphoepitaxy hole processes using contour-based metrology

Significant interest from the integrated circuit (IC) industry has been placed on directed selfassembly (DSA) for sub 10nm nodes. DSA is being considered as a cost reduction complementary process to multiple patterning (MP) and an enabler of new technology nodes. However, to realize the potential of this technology, it is essential to look holistically at the necessary infrastructure from the point of view of materials, hardware, software, process integration and design methodologies which enable its deployment in large volume manufacturing. One key aspect in enabling DSA processes is the ability to mirror functionality of full chip mask synthesis and verification methods of existing tools used in production. One of those critical components is the ability to accurately model the placement of the target phases in the DSA process with a given mask shape, as well as determining the conditions at which unwanted phase transitions start to occur. Self-consistent field theory and Monte Carlo1 simulators have the capability to probe and explore the mechanisms driving the different phases of a diblock copolymer system. While such methods are appropriate to study the nature of the self-assembly process, they are computationally expensive and they cannot be used to perform mask synthesis operations nor full chip verification. The nature of a compact model is to make a series of approximations allowing a simpler description of the problem in a way that the phenomena of interest can be sufficiently captured even if it is at the expense of its generality. In this case we focus our effort in establishing the minimum set of conditions that a compact model for the manufacture of contact holes using a grapho epitaxy process for a PS-PMMA diblock copolymer system needs. The processes uses etched short trenches as guiding patterns in which the vertical DSA cylinders are formed. By focusing in the phase of interest (i.e., cylinder forming conditions), it is possible to reformulate the problem in a phenomenological formulation which accounts for the interaction among cylinders, the volume fraction of the respective co-polymers and the interaction with the confinement walls. As such, a 2D approximation to the 3D environment can be applied too simplify thhe representation of the DSA process. This enables thee use of a 2D contour for compact model training and verification. Further simplification is not recommended due to the nature of the grapho-epitaxy guiding patterns, where a simple CD measurement is not sufficient to capture the 2D environment of post routed contact patterns for sub 10nm nodes. In this paper, we will study the application of the DSA compact model to a via layer of imec’s 7nm technology node standard cells. ArF immersion lithography will be used to pattern the guides, and the layout will be DSA compliant to determine the mask complexity as well as the sensitivity of the solution to mask biases for the contact layer.

Physical verification and manufacturing of contact/via layers using grapho-epitaxy DSA processes

This paper extends the state of the art by describing the practical material’s challenges, as well as approaches to minimize their impact in the manufacture of contact/via layers using a grapho-epitaxy directed self assembly (DSA) process. Three full designs have been analyzed from the point of view of layout constructs. A construct is an atomic and repetitive section of the layout which can be analyzed in isolation. Results indicate that DSA’s main benefit is its ability to be resilient to the shape of the guiding pattern across process window. The results suggest that directed self assembly can still be guaranteed even with high distortion of the guiding patterns when the guiding patterns have been designed properly for the target process. Focusing on a 14nm process based on 193i lithography, we present evidence of the need of DSA compliance methods and mask synthesis tools which consider pattern dependencies of adjacent structures a few microns away. Finally, an outlook as to the guidelines and challenges to DSA copolymer mixtures and process are discussed highlighting the benefits of mixtures of homo polymer and diblock copolymer to reduce the number of defects of arbitrarily placed hole configurations.

Directed self-assembly graphoepitaxy template generation with immersion lithography

Abstract. We present an optimization methodology for the template designs of subresolution contacts using directed self-assembly (DSA) with graphoepitaxy and immersion lithography. We demonstrate the flow using a 60-nm-pitch contact design in doublet with Monte Carlo simulations for DSA. We introduce the notion of template error enhancement factor (TEEF) to gauge the sensitivity of DSA printing infidelity to template printing infidelity and evaluate optimized template designs with TEEF metrics. Our data show that source mask optimization and inverse lithography technology are critical to achieve sub-80 nm non-L0 pitches for DSA patterns using 193i.

Multi-selection method for physical design verification applications

In this paper we present a modular approach which combines model based verification, pattern matching and machine learning methods in order to achieve a high accuracy over computing time ratio. We utilize pattern recognition technique using a supervised machine learning system (as opposed to pattern matching) to classify the patterns either as failures (hotspots) or non-failures, and we use pattern matching to detect all the outlier misses and false detections in each of the regions (based on the calibration set), which will be added or removed from the set of hotspots later on. Doing so allows us to do two things: Reduce the number of patterns that need to be pattern matched since only the outliers of the machine learning system need to be considered and more importantly it allows us to add trained predictability to new configurations that were not in the training set but that can be interpolated from the system. The results indicate that indeed it is possible to successfully combine Machine learning with pattern matching methods in order to achieve better predictability of errors of previously unseen data, while being exact in the treatment of previously observed data. We also explore possible avenues to further speed up the computation of the layout characterization process by inserting a global density grid, and assess the impact of model quality and aliasing under real detection conditions.