Fengze Hou

Thermal management of 3D RF PoP based on ceramic substrate

In this paper, a new high performance three dimensional radio frequency package on package (3D RF PoP) based on ceramic substrate is designed for micro base station which is able to cover the multicasting of critical messages to as many mobile users as possible even under communications network failure events, such as the failure of macro base stations. The RF PoP integrates receiver (RX) module, transmitter (TX) and digital predistortion (DPD) module, and analog-to-digital/digital-to-analog (AD/DA) and clock (CLK) module vertically, has better signal integrity and faster data-rate transfer due to shorter signal paths among the three modules. Additionally, the ceramic substrate has higher thermo-mechanical reliability and better heat dissipation performance compared with organic substrate. The paper firstly studies the thermal performance of the RF PoP without external heat sinks using commercial software ANSYS Icepak. At the ambient temperature of 25 °C, the highest junction temperature of the RF PoP is 239.8 °C, which is above the acceptable baseline for a silicon chip. Secondly, in order to improve the heat dissipation capability of the RF PoP, a large copper bottom heat dissipation plate is employed. The impact of bottom heat dissipation plate on the thermal performance of the RF PoP is investigated. It is found that a bottom heat dissipation plate of 200×200×2 mm3 is reasonable, and the highest junction temperature is about 47.0 °C. Thirdly, we study the thermal performance of the entire and internal package structure of the RF PoP mounted on the bottom heat dissipation plate. The temperature distributions of the top and middle substrates are almost uniform. Heat generated from active devices on the top and middle packages is mainly transferred to the edges, conducted to the bottom heat dissipation plate through the edges and bottom substrate and heat slug, heat generated from active devices on the bottom package is conducted to the bottom heat dissipation plate through the bottom substrate and heat slug, and then dissipated into the ambient by natural convection, so that the temperature at the edge of the bottom substrate is higher than the other parts. Lastly, the effect of different ambient temperatures on the thermal performance of the RF PoP is investigated. When the bottom heat dissipation plate size is 200×200×2 mm3 and the ambient temperature reaches 100 °C, the highest junction temperature is about 121 °C. In order to further improve heat dissipation capability of the RF PoP, a copper top heat spreader is employed. The simulation result shows that the junction temperature drops to about 115.6 °C.

Thermal characterization of a novel 3D stacked package structure by CFD simulation

In this paper, a novel 3D stacked package structure with horizontal fins is designed to solve the heat dissipation issue. In order to verify the thermal performance, a 3D stacked package test vehicle with five chips and two interposers is built in a CFD software-Icepak. The size of the chip is in accordance with commercial thermal test chip (TTC-1002, TEA). Three different cooling methods of this architecture are studied, including natural convection, forced air convection, and immersion cooling. Temperature profiles under different external conditions are obtained and analyzed to determine the thermal resistances between adjacent chips qualitatively. Due to the increased heat flow paths, the novel 3D stacked package structure with horizontal fins has a better dissipation effect than traditional structure. The cooling capacity of immersion cooling is the best among the three cooling conditions. Through immersion cooling, the hot-spot temperature of this 3D stacked package can be maintained at a low level. The length of the fins is also studied to balance the optimal cooling performance and minimum volume occupancy. The length of the fins is very critical to the optimal cooling performance, especially in natural convection condition and forced air convection condition. The optimal length of the fin should be based on the heat dissipation of chips, the application environment, the reliability and also the costs. This work offers an insight look of thermal management for 3D stacked chips, and this structure is expected to be applied in future electronics.

Thermal-mechanical simulation of embedded module based on organic substrate

Embedded devices encapsulated by electronic packaging offer significant advantages in terms of miniaturization, cost and performance. A new packaging concept, Embedded Technology, is highly conducive to the aforementioned advantages where active components are directly embedded into organic substrates without incurring subsequent package assembly processes such as flip-chip technology. However, one of the most significant drawbacks of Embedded Technology is its inherently poor thermal characteristics, which is symptomatic of most embedded device topologies. This paper presents a practical, streamline thermal management design methodology that mitigates thermal-mechanical risks of Embedded Technology while balancing electrical performance and cost considerations. The proposed methodology first demonstrates that the associated thermal-mechanical weaknesses of Embedded Technology can be mitigated through judicious selection of an appropriate substrate with good thermal conductivity, low Coefficient of Thermal Expansion (CTE) and high degree of hermeticity. A heuristic thermal-mechanical study of an embedded power MOSFET module is exemplified in this paper; its thermal performance is characterized under both steady-state and transient conditions thereby highlighting the embedded modules sensitivity to material properties and convection properties. A power MOSFET bare die from Alpha & Omega Semiconductor Co. is applied in this embedded module. Thermal management characterization of the structure is subsequently scrutinized under different loading conditions, which can be done efficiently by numerical studies based on Finite Element Analyses (FEA). Simulation results reveal that the thermal-mechanical properties of the embedded module under forced-convection are much better compared to the properties under natural-convection. The thermal performance of the embedded module under forced convection conditions is sensitive to changes in temperature. Lastly, thermal-mechanical simulations depict elevated stress concentrations appearing at the central portion of the MOSFET die edge, which could lead to potential brittle fracture. Qualitative correlation of the predicted stress contours with observed cross-sectioned SEM samples demonstrate that mitigating measures can be incorporated into the baseline simulation environment, a priori, to truncate product design iterations and improve process reliability.

A 3D package design with cavity substrate and stacked die

Portable consumer electronics have a tremendous demand of miniaturization, high density and high performance. 3D SIP is an efficient solution to meet this requirement. This paper had presented an innovative 3D package product configured with stacked die and cavity-embedded substrate. Through hole via in the substrate provides the signal communication at a cost-effective way. This structure satisfies the high standards for mobile products packaging by reducing the package size and cost and maintaining functionality. In this paper, some details on the design concepts of the structure are introduced. Then, since the geometric configuration of the bonding wire is unusual, the electrical performance of the wire bonds of the structure is predicted by HFSS. Though the wire bond is long, simulation results shows that it is still suitable for the speed circuits below 3GHz. On the other hand, the two-step cavity effectively improves the isolation capability between different die. Moreover, the fabrication process of this structure is presented in detail to access the design. Finally, the functional test of the end products is performed and the end products work well.

Thermo-mechanical reliability analysis of a RF SiP module based on LTCC substrate

Abstract The RF SiP module based on LTCC substrate has attracted considerable attention in wireless communications for the last two decades. However, the thermo-mechanical reliability of this 3D LTCC architecture has not been well-studied as common as its traditional ceramic package structure. A practical RF SiP module based on LTCC substrate was presented and its thermo-mechanical reliability was analyzed in this paper, with emphasis on the reliability of heat reflow process, the operating state and fatigue of second-level solder joints. The configuration and assembly process of the SiP module were briefly introduced at first, and qualitative analysis was made according to the reliability problem that may occur in the manufacturing process and the operating state. Through FEM simulation, this paper studied the warpage and stress variation of the RF SiP module, as well as parametric studies of some key package dimensions. Solder joint reliability under temperature cycling condition was also analyzed in particular in this paper. The results show that for the heat reflow process and operating state, the maximum warpage is both on the top LTCC substrate, but the maximum stresses are on the outermost solder ball and the kovar column at the corner, respectively. There is a large residual stress on the critical solder ball at the end of the reflow process and the key package dimensions has little effect on it. The thickness of top LTCC substrate has a significant impact on the thermal deformation and thermal stress, followed by the height of kovar columns. The reason for the considerable thermal stress on the kovar column is the non-uniform of temperature distribution. The key to reducing thermal deformation and stress in the operating state is the employment of effective cooling measures. It is found by comparison that the reliability of critical solder joints can be greatly improved by adding suitable underfill.

Optimization Design of 2.5D TSV Package Using Thermo-Electrical Co-Simulation Method

In this paper, a 2.5D TSV (through silicon via) package is de-signed for handheld device. A high performance Application Processor die and a Memory die with the sizes of 7.535×7.616×0.15 mm3 and 7.336×3.604×0.15 mm3, respectively, are integrated on a silicon interposer with a large number of TSVs. The backside and front of the interposer have one and two layers of redistribution layer (RDL), respectively. Each layer of RDL is about 3~5 μm and the minimum line width / pitch of the RDL in the interposer are 10 μm / 10 μm. In order to investigate the thermal performance of the package, IR drop of Power and Ground (P/G) Nets of the Processor and Memory dies, and the mutual effects of them, the paper conducts the following researches: First of all, only thermal simulation is done to investigate the thermal performance of the 2.5D TSV package using Cadence Sigrity PowerDC. The highest junction temperatures of Processor and Memory dies are evaluated. When the ambient temperature is 25°C, the junction temperatures of Processor and Memory dies are 62.7°C and 56°C, respectively, which are relatively higher for handheld device. Then, thermal and optimization designs are conducted to improve the thermal performance of the 2.5D TSV package. An aluminum heat spreader is employed, attached to the top surface of the 2.5D TSV package through high heat conductive thermal interface material (TIM). The effects of heat spreader size on the highest junction temperatures of Processor and Memory dies are studied and a heat spreader size of 60×60×2 mm3 is chosen. Thirdly, thermal simulation and thermo-electrical co-simulation are compared to study the effects of P/G Nets of the both dies on the thermal performance of the 2.5D TSV package. It is found that P/G Nets could increase the junction temperature of the both dies. Fourthly, IR drop analysis and thermo-electrical co-simulation are compared to study the effects of the heat dissipation issues of the package on the IR drop of P/G Nets of the both dies. The study shows that the heat could increase the IR drop of P/G Nets of the both dies and IR drop of VDDCPU of the Processor die is the biggest. Fifthly, aiming at the VDDCPU of Processor die, optimization design is carried out to reduce the IR drop of VDDCPU. After optimization, IR drop of VDDCPU decreases by 45.3%. IR drop decreases to an acceptable value. Therefore, P/G Nets of the dies should be considered when conducting thermal simulation of the package, and heat dissipation issues of the package should also be considered when analyzing IR drop of P/G Nets of the dies.

Design and implementation of two different RF SiPs for micro base station

Today a range of wireless communication products have the requirement of achieving a higher integration level. In this paper, we propose two RF SiPs based on a RF prototype board for micro base station. The two RF SiPs integrate a complete 700-2600MHz RF system that includes transmitter, receiver, and feedback module, ADC/DAC and clock module. RF SiP 1 consists of two multilayer organic substrates, which are vertically stacked by using Ball BGA interconnections. RF SiP 2 uses flexible substrate as the interconnections between the top and the bottom substrates. Compared with the original RF part on the prototype board (20cm×25cm), the size of the two RF SiPs is 5.25m×5.25cm, almost reducing system area 20 times. By comparison, the flexible substrate on RF SiP 2 provides better transmission quality of input RF signals and RF SiP 2 shares better thermal performance. Besides, the RF SiP 1 uses more conventional processes and has the potential to be fabricated with a lower cost.

Temperature-dependant thermal stress analysis of through-silicon-vias during manufacturing process

Thermal stress is induced by high temperature manufacturing processes, due to the mismatch of Coefficient of Thermal Expansion s (CTE) between silicon, dielectric material and copper. In this paper, thermal stress around Through-Silicon-Vias (TSVs) was discussed using 3D FEA transient method. Stress distributions near a TSV and TSVs array were investigated after dielectric liner deposition, barrier layer deposition and annealing process, respectively. Moreover, stress distribution around a via was impacted by the thickness of the dielectric liner, the via diameter, the via pitch and the cooling speed during annealing process. In order to verify the simulation results, TSV samples were fabricated through a series of processes. Si Raman shift profiles near a TSV was also measured and calculated. The simulation results coincided with the real measurement value in tolerable error range.

The design for manufacture of high density DSP package

The mania for mobility applications such as smart-phones, tablet PCs, and personal computers is sweeping all over the globe. In order to insure the performance of a new product, the Design for Manufacture (DFM) plays an important role on a package design both in research stage and mass product stage. The substrate process capabilities, assembly process capabilities, material properties, and package structure are the main factors for DFM. In this paper, a high density DSP (Digital Signal Processing) package is showed as an example for the DFM methodology. For this typical high density WB-BGA package, the warpage control is the key point for DFM not only in substrate process but also in assembly process. The molding compound (MC) is used for protecting die. Molding or dispending process is the main step for assembly process. The coefficient of thermal expansion (CTE) mismatch and the material shrinkage cause the substrate deformation. If the substrate deformation large enough, it will affect cold solder joint between substrate and PCB (Printed Circuit Board), and the electrical performance and reliability. To evaluate the deformation by molding or dispensing process, the cooling down stage from 125 °C to 25 °C was simulated by EDA tool. The warpage of test samples with different molding height were measured here to estimate the real DSP package design. The difference of simulation data and measurement data are little. If the molding height is large enough, the structure deformation mainly depends on the molding structure. To improve the warpage, a copper ring is used in dispensing technology for DSP package. The significant signals were tested by oscilloscope and logic analyzer to verify the performance of DSP package, and the performance of the DSP was satisfied with the target.

Reliability research on optoelectronics packaging

Optoelectronic packaging is a challenge for optoelectronic device and optoelectronic integration. In the packaging level, optical under fill compound, optical fiber array, micro lens, silicon carrier and substrate effects on the thermal, optical and reliability performance of optoelectronic packaging. To prepare this challenge, a wide range of analysis and expertise for integrated optoelectronics, thermal and power management should be done. In this paper, reliability quality is researched based on parallel optical transceiver SiP. Then glue including under fill compound, optical fiber fixed and wire bonding glue is tested under 85 ° C/85 RH and -40 to 85° C thermal shock conformed with TELCORDIA standard. Also dielectric constant is measured for high frequency application. A 8 channel transceiver is fabricated with 80Gbps two way bandwidth. The eye diagram of 10Gbps of transceiver is tested from 25 to 60° C. Some results are discussed and some suggestion given is helpful on design of the reliability of optoelectronic packaging.