Pablo Royer

Real-time low-complexity automatic modulation classifier for pulsed radar signals

An automatic modulation classifier (AMC) based on low-complexity signal features and a hierarchical decision tree is presented for pulsed radar applications. This AMC is implemented on a field-programmable gate array (FPGA) platform. The algorithm has been designed to minimize the computational burden to achieve real-time operation. The novelty of the paper consists of the development of a low-computational-complexity radar AMC suitable for real-time FPGA implementation.

Using pMOS Pass-Gates to Boost SRAM Performance by Exploiting Strain Effects in Sub-20-nm FinFET Technologies

Strained fin is one of the techniques used to improve the devices as their size keeps reducing in new nanoscale nodes. In this paper, we use a predictive technology of 14 nm where pMOS mobility is significantly improved when those devices are built on top of long, uncut fins, while nMOS devices present the opposite behavior due to the combination of strains. We explore the possibility of boosting circuit performance in repetitive structures where long uncut fins can be exploited to increase fin strain impact. In particular, pMOS pass-gates are used in 6T complementary SRAM cells (CSRAM) with reinforced pull-ups. Those cells are simulated under process variability and compared to the regular SRAM. We show that when layout dependent effects are considered the CSRAM design provides 10% to 40% faster access time while keeping the same area, power, and stability than a regular 6T SRAM cell. The conclusions also apply to 8T SRAM cells. The CSRAM cell also presents increased reliability in technologies whose nMOS devices have more mismatch than pMOS transistors.

Evolution of radiation-induced soft errors in FinFET SRAMs under process variations beyond 22nm

New CMOS technologies such as SOI or FinFET are expected to enhance SRAM radiation-induced soft error rates thanks to a reduction on the charge collected as the devices get smaller. In this work we analyze how the radiation hardening capabilities of SRAMs are affected when process variations are considered by simulating cells using a predictive FinFET technology. The results show that even if the average critical charge to which SRAM cells are vulnerable is enhanced by process variations, its widened spread leads to an increase of the soft error rate by more than 40% as the technology node is scaled down to 7nm.

A tool for the automatic analysis of single events effects on electronic circuits

Nowadays integrated circuit reliability is challenged by both variability and working conditions. Environmental radiation has become a major issue when ensuring the circuit correct behavior. The required radiation and later analysis performed to the circuit boards is both fund and time expensive. The lack of tools which support pre-manufacturing radiation hardness analysis hinders circuit designers tasks. This paper describes an extensively customizable simulation tool for the characterization of radiation effects on electronic systems. The proposed tool can produce an in depth analysis of a complete circuit in almost any kind of radiation environment in affordable computation times.

Reconfigurable Writing Architecture for Reliable RRAM Operation in Wide Temperature Ranges

Resistive switching memories [resistive RAM (RRAM)] are an attractive alternative to nonvolatile storage and nonconventional computing systems, but their behavior strongly depends on the cell features, driver circuit, and working conditions. In particular, the circuit temperature and writing voltage schemes become critical issues, determining resistive switching memories performance. These dependencies usually force a design time tradeoff among reliability, device endurance, and power consumption, thereby imposing nonflexible functioning schemes and limiting the system performance. In this paper, we present a writing architecture that ensures the correct operation no matter the working temperature and allows the dynamic load of application-oriented writing profiles. Thus, taking advantage of more efficient configurations, the system can be dynamically adapted to overcome RRAM intrinsic challenges. Several profiles are analyzed regarding power consumption, temperature-variations protection, and operation speed, showing speedups near

Implementation tradeoffs of triangle traversal algorithms for graphics processing

700\times

Circuit-level modeling of FinFet sub-threshold slope and DIBL mismatch beyond 22nm

compared with other published drivers.

Architecture, design and technology guidelines for crosspoint memories

Current CPU architectures provide high processing rates in graphical applications because of their specialized graphics pipeline. So far, little attention has been paid in the scientific literature to the analysis and study of different hardware structures that implement specific pipeline stages. In this work we have identified one of the key stages in the graphics pipeline, the triangle traversal procedure, and we have implemented it in a 90 nm standard cell technology, comparing three different algorithms: Bounding-box, Zig-zag and Hilbert curve-based. The experimental results show that important area-latency-frequency-throughput tradeoffs must be taken into account for the implementation of the triangle traversal stages. Furthermore, since power is a main concern in CPUs, we have studied how some triangle characteristics such as the shape, size, position and depth affect the power consumption.

Four-injector variability modeling of FinFET predictive technology models

We propose a way of modeling device variability in sub-threshold slope and DIBL at circuit-level using dependent voltage sources. The usual way of modeling variability using threshold voltage shift and drain current amplification is becoming inaccurate as new sources of variability appear in sub-22nm devices. Benchmark experiments on circuit level, using a set of 1000 TCAD-based 10nm-FinFet device models with mismatch as a reference, show systematic accuracy improvements on mean and standard deviation of 6T-SRAM cell stability metrics of up to 30 and 10 percentage scores, respectively.

A low power 6t-SRAM using negative bit-line for variability tolerance beyond 22nm node

While standalone Flash memories (NAND) are facing their physical limitations, the emergence of resistive switching memories (RRAM) is seen as a solution for high density, low cost and low energy NAND replacement candidate. However, it has been shown that deeply scaled, high density RRAM architectures, such as crosspoint, suffer of voltage drop effects (IR drop) in metal lines, periphery overhead and metal line charging time due to injected current during programming operations and sneaking currents through unselected bitcells. In this work, we first propose several innovative models for IRdrop, periphery overhead and array-line charging time accounting for in-array multiple bit-write operation. Then, we introduce a new methodology for crosspoint memory design to determine IRdrop, periphery overhead and timing associated with the optimal characteristics of 1 selector-1 resistance (ISIR) device. We apply the proposed methodology to various half metal pitch memory technology nodes (from 50nm to 15nm) and to several written word sizes (from 1 to 32 bits). We show that for 1 bit programmed per array, the RRAM programming current has to be lower than 30μΑ and the selector leakage current lower than 10nA and that limitations increase as soon as multiple bits are written simultaneously in the same array. This, suggests massively parallel multi-bank write of a small number of bits per array, as the best solution for the RRAM memories to be competitive with NAND memories.