Lars W. Liebmann

Layout impact of resolution enhancement techniques: impediment or opportunity?

This tutorial introduces the reader to the basic concepts of optical lithography, derives fundamental resolution limits, reviews the challenges facing future technology nodes, explains the principles of resolution enhancement techniques and their impact on chip layout, and discusses layout optimization considerations.

Lithographic comparison of assist feature design strategies

Subresolution assist features, when used in conjunction with off-axis illumination, have shown great promise for reducing proximity effects while improving lithographic process window. However, these patterns result in an increased emphasis on the mask manufacturing process, primarily in the areas of mask writing and inspection. In choosing a design strategy, one must be careful to account for the mask making capabilities, such as write tool grid size and linearity, along with the lithographic effect of errors in the mask making process. In addition to mask errors, stepper lens aberrations and expected process variations can also have a large influence on design rules. Generally, design tradeoffs must be made to balance the impact of these for the best overall lithographic performance.

TCAD development for lithography resolution enhancement

Advances in lithography have contributed significantly to the advancement of the integrated circuit technology. While nonoptical next-generation lithography (NGL) solutions are being developed, optical lithography continues to be the workhorse for high-throughput very-large-scale integrated (VLSI) lithography. Extending optical lithography to the resolution levels necessary to support today’s aggressive product road maps increasingly requires the use of resolution-enhancement techniques. This paper presents an overview of several resolution-enhancement techniques being developed and implemented in IBM for its leading-edge CMOS logic and memory products.

Integrating DfM components into a cohesive design-to-silicon solution (Invited Paper)

Two primary tracks of DfM, one originating from physical design characterization, the other from low-k1 lithography, are described. Examples of specific DfM efforts are given and potentially conflicting layout optimization goals are pointed out. The need for an integrated DfM solution than ties together currently parallel DfM efforts of increasing sophistication and layout impact is identified and a novel DfM-enabling design flow is introduced.

High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell

A high performance 65 nm SOI CMOS technology is presented featuring 35 nm gate length, 1.05 nm gate oxide, performance enhancement from dual stress nitride liners (DSL), and 10 wiring levels with low-k dielectric offered in the first 8 levels. DSL enhancement is shown to scale well to 65 nm with larger enhancement seen than at 90 nm design rules. A high performance 0.65/spl mu/m/sup 2/ SRAM cell is also presented. SOI allows the SRAM cell to use Metal 1 instead of Metal 2 for bit-line wiring, which lowers the capacitance and improves access times. A functional dual-core microprocessor test chip containing 76Mb SRAM cache and key execution units has been fabricated.

Pattern-dependent correction of mask topography effects for alternating phase-shifting masks

Strategies for modifying both mask fabrication processes and design data for alternating phase-shifting masks to account for mask scattering phenomena are explored. Results were derived from the rigorous solution of Maxwells equations using the EMFlex and TEMPEST programs for an etched-quartz fabrications process. By importing the resulting diffracted orders into VCIMAGE, full vector calculation of the aerial image from mask to wafer was obtained. From the rigorous mask simulations, the 0th and 1st diffracted orders were translated into an effective transmission and phase based on a thin-mask approximation. With this analysis technique, a 0.25 micrometers line-space grating for the baseline etched-quartz process (4X magnification) showed a transmission error of 7.2% and a phase error of 1.6 degree(s). In order to compensate for these errors, etch-back fabrication techniques, in which the quartz was recessed beneath the chrome, were evaluated to determine the extent to which the transmission and phase errors could be reduced. For the dual etch-back process typically in use today, a residual transmission error of approximately 0.5% could not be completely removed, even for etch-back depths greater than 200 nm. Correction of the phase errors was achieved by reducing the reactive-ion etch depth by 2-3 nm. Design manipulation, in which the 180 degree(s) opening was increased in size, required feature-dependent phase errors as large as 1 degree(s) were present.

Compensating non-optical effects using electrically driven optical proximity correction

Chip performance and yield are increasingly limited by systematic and random variations introduced during wafer processing. Systematic variations are layout-dependent and can be broadly classified as optical or non-optical in nature. Optical effects have their origin in the lithography process including mask, RET, and resist. Non-optical effects are layout-dependent systematic variations which originate from processes other than lithography. Some examples of nonoptical effects are stress variations, well-proximity effect, spacer thickness variations and rapid thermal anneal (RTA) variations. Semiconductor scaling has led to an increase in the complexity and impact of such effects on circuit parameters. A novel technique for dataprep called electrically-driven optical proximity correction (ED-OPC) has been previously proposed which replaces the conventional OPC objective of minimization of edge placement error (EPE) with an electrical error related cost function. The introduction of electrical objectives into the OPC flow opens up the possibility of compensating for electrical variations which do not necessarily originate from the lithographic process. In this paper, we propose to utilize ED-OPC to compensate for optical as well as non-optical effects in order to mitigate circuit-limited variability and yield. We describe the impact of non-optical effects on circuit parameters such as threshold voltage and mobility. Given accurate models to predict variability of circuit parameters, we show how EDOPC can be leveraged to compensate circuit performance for matching designer intent. Compared to existing compensation techniques such as gate length biasing and metal fills, the primary advantage of using ED-OPC is that the process of fragmentation in OPC allows greater flexibility in tuning transistor properties. The benefits of using ED-OPC to compensate for non-optical effects can be observed in reduced guard-banding, leading to less conservative designs. In addition, results show a 4% average reduction in spread in timing in compensating for intra-die threshold voltage variability, which potentially translates to mitigation of circuit-limited yield.

Lithographic effects of mask critical dimension error

Magnification of mask dimensional error is examined and quantified in terms of the mask error factor (MEF) for line and hole patterns on three types of masks: chrome-on-glass (COG), attenuated phase-shifting mask (PSM) and alternating PSM. The MEF is unity for large features, but increases rapidly when the critical dimension (CD) is less than 0.5 (lambda) /NA for line-space patterns and 0.75 (lambda) /NA for contacts. In general dark-field spaces exhibit higher sensitivity to mask dimensional error than light-field lines. Sensitivity of attenuated PSMs is similar to COG masks, even for applications in which attenuated PSMs provide benefits in process latitude. Alternating PSMs have the lowest MEF values. Although the MEF has only a slight dependence on feature nesting for contacts, dense lines and spaces exhibit markedly higher MEF values than isolated features. The MEF of a 0.35 (lambda) /NA isolated line is 1.6 whereas that of a dense line of the same dimension is 4.3 illumination is effective in reducing the mask error sensitivity of dense lines. Dose variation causes changes in the MEF of contacts but has little effect on line-space features; focus error degrades (increases the value of) the MEF of both pattern types. A high diffusion and low contrast photoresist process also worsens the MEF. Consequences of mask CD error amplification include tightening of mask specification, design grid reduction, shift in optimal mask bias and enhanced defect printability.

Electrically driven optical proximity correction

Existing optical proximity correction tools aim at minimizing edge placement errors (EPE) due to the optical and resist process by moving mask edges. However, in low-k1 lithography, especially at 45nm and beyond, printing perfect polygons is practically impossible to achieve in addition to incurring prohibitively high mask complexity and cost. Given the impossibility of perfect printing, we argue that aiming to reduce the error of electrical discrepancy between the ideal and the printed contours is a more reasonable strategy. In fact, we show that contours with non-minimal EPE may result in closer match to the desired electrical performance. Towards achieving this objective, we developed a new electrically driven OPC (ED-OPC) algorithm. The tool combines lithography simulation with an accurate contour-based model of shape electrical behavior to predict the on/off current through a transistor gate. The algorithm then guides edge movements to minimize the error in current, rather than in edge placement, between current values for printed and target shapes. The results on industrial 45nm SOI layouts using high-NA immersion lithography models show up to a 5% improvement in accuracy of timing over conventional OPC, while at the same time showing up to 50% reduction in mask complexity for gate regions. The results confirm that better timing accuracy can be achieved despite larger edge placement error.

Application of the aerial image measurement system (AIMS)TM to the analysis of binary mask imaging and resolution enhancement techniques

The newly developed Aerial Image Measurement System (AIMSTM*) was used to quantify the lithographic benefits of several resolution enhancement techniques as compared to standard binary mask imaging. This system, a microscope based stepper emulator, permits rapid characterization of mask images from both binary and phase shifted mask (PSM) patterns at multiple focal planes. The resultant images are captured digitally with a CCD camera and analyzed using an exposure-defocus tree technique to quantify the depth-of-focus as a function of exposure latitude. The AIMS is used to extract both phase and transmission errors from captured aerial images of all the masks evaluated. AIMS results are compared to wafer electrical linewidth data. A 0.5 numerical aperture (NA) DUV stepper was used with a partial coherence of 0.6 combined with IBM APEX-E resist process. Collected data were analyzed using techniques identical to the AIMS analysis, allowing for a high level of consistency. Comparative data focused on binary mask imaging for the verification of the AIMS results. Trends associated with feature sizes and types are discussed.