Francesco Radice

3.6 A 45Gb/s PAM-4 transmitter delivering 1.3Vppd output swing with 1V supply in 28nm CMOS FDSOI

The development of next-generation electrical link technology to support 400Gb/s standards is underway [1-5]. Physical constraints paired to the small area available to dissipate heat, impose limits to the maximum number of serial interfaces and therefore their minimum speed. As such, aggregation of currently available 25Gb/s systems is not an option, and the migration path requires serial interfaces to operate at increased rates. According to CEI-56G and IEEE P802.3bs emerging standards, PAM-4 signaling paired to forward error correction (FEC) schemes is enabling several interconnect applications and low-loss profiles [1]. Since the amplitude of each eye is reduced by a factor of 3, while noise power is only halved, a high transmitter (TX) output amplitude is key to preserve high SNR. However, compared to NRZ, the design of a PAM-4 TX is challenged by tight linearity constraints, required to minimize the amplitude distortion among the 4 levels [1]. In principle, current-mode (CM) drivers can deliver a differential peak-to-peak swing up to 4/3(VDD-VOV), but they struggle to generate high-swing PAM-4 levels with the required linearity. This is confirmed by recently published CM PAM-4 drivers, showing limited output swings even with VDD raised to 1.5V [2-4]. Source-series terminated (SST) drivers naturally feature better linearity and represent a valid alternative, but the maximum differential peak-to-peak swing is bounded to VDD only. In [5], a dual-mode SST driver supporting NRZ/PAM-4 was presented, but without FFE for PAM-4 mode. In this paper, we present a PAM-4 transmitter leveraging a hybrid combination of SST and CM driver. The CM part enhances the output swing by 30% beyond the theoretical limit of a conventional SST implementation, while being calibrated to maintain the desired linearity level. A 5b 4-tap FIR filter, where equalization tuning can be controlled independently from output matching, is also embedded. The transmitter, implemented in 28nm CMOS FDSOI, incorporates a half-rate serializer, duty-cycle correction (DCC), ≫2kV HBM ESD diodes, and delivers a full swing of 1.3Vppd at 45Gb/s while drawing 120mA from a 1V supply. The power efficiency is ~2 times better than those compared in this paper.

Analysis and Design of a Power-Scalable Continuous-Time FIR Equalizer for 10 Gb/s to 25 Gb/s Multi-Mode Fiber EDC in 28 nm LP CMOS

A continuous-time 7-tap FIR equalizer tailored to dispersion compensation in multi-mode fiber links is presented. By using a novel active delay line, the ultra-compact equalizer is very flexible, maintaining optimal performances and power scalability over a wide range of input data-rates. Particular care is taken to address critical issues of continuous-time realizations, such as noise, linearity and dynamic range. All-pass stages, realized with a simple circuit topology featuring high linearity and wide bandwidth, are investigated to implement the active delay line elements. Filter tap coefficients are realized with programmable transconductors and output currents are summed through a transimpedance amplifier, providing simultaneously high gain and wide bandwidth. Extensive experimental results, carried out on test chips realized in 28 nm LP CMOS technology, are presented. The equalizer demonstrates successful operation with variable data-rates ranging from 10 Gb/s to 25 Gb/s and power dissipation scalable from 55 mW to 90 mW. Compared to previously reported high-speed FIR equalizers, the proposed solution accepts the largest variation of the input data-rate with state-of-the-art power efficiency and core silicon area of only 0.085 mm 2, meeting the demand of emerging 400 Gb/s standards.

A High-Swing 45 Gb/s Hybrid Voltage and Current-Mode PAM-4 Transmitter in 28 nm CMOS FDSOI

Pushed by the ever-increasing demand of high-speed connectivity, next generation 400 Gb/s electrical links are targeting PAM-4 modulation to limit channel loss and preserve link budget. Compared to NRZ, a higher amplitude is desirable to counteract the 1/3 reduction of PAM-4 vertical eye opening. However, linearity is also key, and PAM-4 levels must be precisely spaced to preserve the horizontal eye opening advantage it has over NRZ. This paper presents a 45 Gb/s PAM-4 transmitter able to deliver a very large output swing with enhanced linearity and state-of-the-art efficiency. Built around a hybrid combination of current-mode and voltage-mode topologies, the driver is embedded into a 4-taps 5-bits feed-forward equalizer (FFE), and allows tuning the output impedance to ensure good source termination. Implemented in 28 nm CMOS FDSOI process, the full transmitter includes a half-rate serializer, duty-cycle correction circuit, >> 2 kV HBM ESD diodes, and delivers a full swing of 1.3 Vppd at 45 Gb/s, while drawing only 120 mA from 1 V supply. The power efficiency is ~ 2 times better than previously reported PAM-4 transmitters.

8.3 A power-scalable 7-tap FIR equalizer with tunable active delay line for 10-to-25Gb/s multi-mode fiber EDC in 28nm LP-CMOS

Multi-mode fiber (MMF) is the most cost-effective fiber for high-speed LANs. Modal dispersion leads to optical-energy spreading over several symbol periods, drastically limiting distance and data-rate. Compared with copper channels, equalization is challenging because the channel response varies enormously from fiber to fiber and also over time [1]. These aspects, paired with the practical difficulty of implementing TX pulse shaping, increase the equalization burden at the receiver. To date, electronic dispersion compensation (EDC) consisting of an FIR filter cascaded with a nonlinear equalizer, such as DFE, enables 10Gb/s up to 300m according to the 10GBASE-LRM standard. To satisfy the demand for greater network capacity, solutions to reach 25Gb/s on a single fiber, and up to 400Gb/s aggregated throughput with space-division multiplexing on 16 fibers are being investigated [2]. At this data-rate, robust DSP-based EDCs still need high power, indicating an analog approach to signal processing to reduce power. To have market impact and economic feasibility, the interface must be flexible, accommodating a variable data-rates for compatibility with legacy channels and different standards [2]. In addition, achieving high energy efficiency at each standard (i.e., data rate) is fundamental.

A 25-Gb/s FIR equalizer based on highly linear all-pass delay-line stages in 28-nm LP CMOS

FIR filters are attractive to enhance the equalization performances of high speed wireline receivers, providing high flexibility to match the channel frequency response and compatibility with simple adaptation techniques. This paper presents a 25-Gb/s 4-tap FIR equalizer in 28-nm LP CMOS. To keep high SNR and not compromise equalization performances, a new all-pass stage is proposed to realize a delay line accommodating large input signal amplitude. The chip draws 25 mA from 1V supply and measurements with 900 mVpk-pk input signal prove equalization of a 20-dB loss channel with 50% horizontal eye opening at BER=10-12. Experimental results compare favorably against state of the art.

A low-noise programmable-gain amplifier for 25 Gb/s multi-mode fiber receivers in 28nm CMOS FDSOI

Wide bandwidth, very low noise and high gain, finely adjustable, are key features in programmable-gain amplifiers (PGA) employed in multi-mode fiber (MMF) receivers. High frequency boost at Nyquist is also desirable to partially recover ISI and relax the requirements of electronic dispersion compensation. In this work, a PGA for 25Gb/s MMF receivers is proposed. Shunt and series inductors between cascaded stages are exploited to achieve programmable high-frequency boost independent from in-band gain and with a sharp out-of-band roll-off. Compared to typical RC-degenerated gain stages, the adopted solution enables very low noise operation. Realized in 28nm CMOS FDSOI technology the PGA has a programmable gain ranging from 15dB to 29dB with 0.15 dB fine steps and up to 14.2dB boost at Nyquist frequency. Power consumption is 32mW and equivalent input noise, at maximum high-frequency boost, is 300μVrms only.

A 6-bit 6-GS/s 95mW background calibrated flash ADC with integrating preamplifiers and half-rate comparators in 32nm LP CMOS

A 6-bits 6-GS/s flash ADC is presented. Single-stage integrators are proposed as preamplifiers to drive the comparators. Compared to single-stage voltage amplifiers, integrators limit the gain-bandwidth requirements leading to lower power dissipation and smaller device size. Comparators are interleaved and clocked at half rate, limiting dissipation thanks to the longer available regeneration time. Offsets of the front-end are continuously calibrated in background. The ADC, realized in a 32nm Low Power CMOS technology proves a very robust operation with SNDR degradation of only 1.5dB going from 1GS/s to 6GS/s. ENOB at 6GS/s with Nyquist frequency input is 5.25 with power dissipation of 95mW from 1V supply. The corresponding FoM is 416fJ/conv. To the Authors knowledge the converter displays also the highest speed among CMOS flash ADCs with more than 4 effective bits of resolution.