Simone Erba

3.6 A 45Gb/s PAM-4 transmitter delivering 1.3Vppd output swing with 1V supply in 28nm CMOS FDSOI

The development of next-generation electrical link technology to support 400Gb/s standards is underway [1-5]. Physical constraints paired to the small area available to dissipate heat, impose limits to the maximum number of serial interfaces and therefore their minimum speed. As such, aggregation of currently available 25Gb/s systems is not an option, and the migration path requires serial interfaces to operate at increased rates. According to CEI-56G and IEEE P802.3bs emerging standards, PAM-4 signaling paired to forward error correction (FEC) schemes is enabling several interconnect applications and low-loss profiles [1]. Since the amplitude of each eye is reduced by a factor of 3, while noise power is only halved, a high transmitter (TX) output amplitude is key to preserve high SNR. However, compared to NRZ, the design of a PAM-4 TX is challenged by tight linearity constraints, required to minimize the amplitude distortion among the 4 levels [1]. In principle, current-mode (CM) drivers can deliver a differential peak-to-peak swing up to 4/3(VDD-VOV), but they struggle to generate high-swing PAM-4 levels with the required linearity. This is confirmed by recently published CM PAM-4 drivers, showing limited output swings even with VDD raised to 1.5V [2-4]. Source-series terminated (SST) drivers naturally feature better linearity and represent a valid alternative, but the maximum differential peak-to-peak swing is bounded to VDD only. In [5], a dual-mode SST driver supporting NRZ/PAM-4 was presented, but without FFE for PAM-4 mode. In this paper, we present a PAM-4 transmitter leveraging a hybrid combination of SST and CM driver. The CM part enhances the output swing by 30% beyond the theoretical limit of a conventional SST implementation, while being calibrated to maintain the desired linearity level. A 5b 4-tap FIR filter, where equalization tuning can be controlled independently from output matching, is also embedded. The transmitter, implemented in 28nm CMOS FDSOI, incorporates a half-rate serializer, duty-cycle correction (DCC), ≫2kV HBM ESD diodes, and delivers a full swing of 1.3Vppd at 45Gb/s while drawing 120mA from a 1V supply. The power efficiency is ~2 times better than those compared in this paper.

A multi standard 1.5 to 10Gb/s latch-based 3-tap DFE receiver with a SSC tolerant CDR for serial backplane communication

A 1.5 to 10 Gb/s SATA/SAS/FC receiver in 65 nm CMOS is presented. It is based on an adaptive 3-tap latch-based DFE data recovery with self-aligning capability and on an early-late digital clock recovery capable of SSC tracking. Extensive digital features allow self-calibration and eye analysis. The macro measures 0.3 mm2 and consumes 140 mA from 1 V at 8.5 Gb/s.

A High-Swing 45 Gb/s Hybrid Voltage and Current-Mode PAM-4 Transmitter in 28 nm CMOS FDSOI

Pushed by the ever-increasing demand of high-speed connectivity, next generation 400 Gb/s electrical links are targeting PAM-4 modulation to limit channel loss and preserve link budget. Compared to NRZ, a higher amplitude is desirable to counteract the 1/3 reduction of PAM-4 vertical eye opening. However, linearity is also key, and PAM-4 levels must be precisely spaced to preserve the horizontal eye opening advantage it has over NRZ. This paper presents a 45 Gb/s PAM-4 transmitter able to deliver a very large output swing with enhanced linearity and state-of-the-art efficiency. Built around a hybrid combination of current-mode and voltage-mode topologies, the driver is embedded into a 4-taps 5-bits feed-forward equalizer (FFE), and allows tuning the output impedance to ensure good source termination. Implemented in 28 nm CMOS FDSOI process, the full transmitter includes a half-rate serializer, duty-cycle correction circuit, >> 2 kV HBM ESD diodes, and delivers a full swing of 1.3 Vppd at 45 Gb/s, while drawing only 120 mA from 1 V supply. The power efficiency is ~ 2 times better than previously reported PAM-4 transmitters.

An inductor-less 13.5-Gbps 8-mW analog equalizer for multi-channel multi-frequency operation

A low-power analog equalizer has been realized in 45nm CMOS technology. Active feedback is employed to avoid inductors and save chip area. Peaking frequency and gain boost can be finely controlled from 4GHz to 7GHz and from 0dB to 24dB to allow multi-channel multi-frequency operation. The circuit dissipates 8mW from a 1.1V supply and it occupies 0.009mm2. The measured maximum peak-to-peak jitter was 29ps for a 13.5Gb/s data transmission over a 18dB-loss backplane.

A 25-Gb/s FIR equalizer based on highly linear all-pass delay-line stages in 28-nm LP CMOS

FIR filters are attractive to enhance the equalization performances of high speed wireline receivers, providing high flexibility to match the channel frequency response and compatibility with simple adaptation techniques. This paper presents a 25-Gb/s 4-tap FIR equalizer in 28-nm LP CMOS. To keep high SNR and not compromise equalization performances, a new all-pass stage is proposed to realize a delay line accommodating large input signal amplitude. The chip draws 25 mA from 1V supply and measurements with 900 mVpk-pk input signal prove equalization of a 20-dB loss channel with 50% horizontal eye opening at BER=10-12. Experimental results compare favorably against state of the art.

A 12Gb/s 39dB loss-recovery unclocked-DFE receiver with bi-dimensional equalization

Backplane communications are rapidly moving beyond 10 Gb/s both in networking and in hard-disk drive interconnection. Decision Feedback Equalization (DFE) and Duobinary (DB) prove to be effective techniques assuring signal integrity in the presence of ISI, but with speed increase the accuracy of the timing recovery brings additional challenges. Half-rate clock DFEs by loop-unrolling are widely applied to avoid feeding back the decided bit within a 1-bit (UI) time, but the alternated eye opening that is created requires an increased circuit complexity to obtain the maximum accuracy in timing recovery [1][2][3]. DB alternative may suffer in the presence of long sequences of incoming toggle patterns (1010…). In fact, in DB the channel frequency response is pre-shaped into a target shape, but toggle patterns are converted into a constant level, thus not providing information to the timing loop [2][4].

6.4 A 64Gb/s PAM-4 transmitter with 4-Tap FFE and 2.26pJ/b energy efficiency in 28nm CMOS FDSOI

Electrical link migration requires serial interfaces to operate at increasing data rates. Despite the fact that most standards still employ NRZ, practical signal integrity constraints demand PAM-4 modulation, especially for some interconnect applications and low-loss profiles [1]. Nevertheless, compared to NRZ, the design of high-speed PAM-4 transmitters entails several challenges. Achieving high linearity without reducing the output amplitude is key to preserve high SNR, which is tightened by the intrinsic 1/3 eye amplitude reduction. Moreover, transitions between non-adjacent levels reduce horizontal eye openings, demanding wide bandwidth and tight timing constraints. In light of the above issues, pushing the transmitter to high data-rates while maintaining signal integrity and energy efficiency is challenging. In fact, published PAM-4 transmitters [2–5] do not meet the CEI-56G-PAM4 standard [1], requiring up to 56Gb/s and 4-taps of feedforward equalization (FFE). To reach the target, improvements on both the architecture and the circuit side are required. A serializer architecture is presented in this paper. To save power, clocking signals are generated and distributed at quarter-rate, but the last stage employs 2∶1 multiplexers (MUXs) driven by half-rate clocks generated locally to overcome the speed limitation of 4∶1 MUXs. Moreover, a new current-mode driver allows high swing and good linearity by raising the power supply without compromising speed and reliability, and a double T-coil splits transistors and ESD parasitics to meet the bandwidth requirements for the target data rate.

A 10Gb/s receiver with linear backplane equalization and mixer-based self-aligned CDR

A 65 nm CMOS receiver including a tapered chain linear equalization and a mixer based clock recovery circuit capable of SSC tracking is presented. The proposed architecture works up to 10 Gb/s with transmission channels with more than 20 dB loss at Nyquist, while consuming 110 mA and occupying 0.25 mm2.

A 25mW Highly Linear Continuous-Time FIR Equalizer for 25Gb/s Serial Links in 28-nm CMOS

Thanks to the high flexibility in matching the channel frequency response and the compatibility with simple adaptation techniques, Finite Impulse Response (FIR) filters enhance the equalization performances of high-speed wireline receivers. This paper presents a 25-Gb/s FIR equalizer in 28-nm CMOS. The impact of filter noise and distortion, crucial aspects for an analog implementation, is discussed. A thorough system analysis, aimed at deriving the specifications for circuits design, suggests four taps, with a tap-to-tap delay in the range 0.5–1 UI, as optimal compromise among complexity (hence power dissipation) and equalization performances. To keep high SNR, a new all-pass stage is proposed to realize a delay line suitable for high-speed operation while being able to accommodate large input signal amplitude. Measurements are shown at 25 Gb/s for both Non Return to Zero (NRZ) and Pulse Amplitude Modulation (PAM)-4 signals. With a core power dissipation of 25 mW from 1-V supply, the proposed FIR filter recovers 20- and 9-dB channel loss for NRZ and PAM-4, respectively, with horizontal eye openings of 50% and 30%. Compared with the previously reported FIR filters for wireline links at comparable speed, the proposed realization achieves excellent equalization performance with the best power efficiency of 1 mW/Gb/s.

F5: Wireline transceivers for Mega Data Centers: 50Gb/s and beyond

With the explosive data growth due to HD video content, IoT, and the rapid shift from enterprise to cloud computing, Mega Data Centers have become an essential part of the global network infrastructure. Despite their massive scale, Data Center architectures require software-defined network capability and scalability, with lower latency. Interconnects will need to support diversified media-types, higher data-rates (>50Gb/s per lane), and longer distance (up to 2km) to achieve this and still make economic sense. Once a niche for mainly VCSEL links in HPC, “Optical Ethernet” is now becoming mainstream as interconnects for both MMF and SMF in various fiber configurations are being defined within the standards. Also, copper links including backplane continue to be the interconnect with highest volume. The Forum will cover various wireline transceivers enabling Mega Data Centers such as ADC-based transceivers and Silicon Photonics, and challenges moving forward.