Francesco Stefanni

A SystemC-based framework for modeling and simulation of networked embedded systems

Next-generation networked embedded systems pose new challenges in the design and simulation domains. System design choices may affect the network behavior and network design choices may impact on the system design. For this reason, it is important -at the early stages of the design flow- to model and simulate not only the system under design, but also the heterogeneous networked environment in which it operates. For this purpose, we have exploited a modeling language traditionally used for System design -SystemC- to build a system/network simulator named SystemC Network Simulation Library (SCNSL). This library allows to model network scenarios in which different kinds of nodes, or nodes described at different abstraction levels, interact together. The use of SystemC as unique tool has the advantage that HW, SW, and network can be jointly designed, validated and refined. As a case study, the proposed tool has been used to simulate a sensor network application and it has been compared with NS-2, a well-known network simulator; SCNSL shows nearly two-order-magnitude speed up with TLM modeling and about the same performance as NS-2 with a mixed TLM/RTL scenario. The simulator is partially available to the community at http://sourceforge.net/projects/scnsl/.

HIFsuite: tools for HDL code conversion and manipulation

HIFSuite ia a set of tools and application programming interfaces (APIs) that provide support for modeling and verification of HW/SW systems. The core of HIFSuite is the HDL Intermediate Format (HIF) language upon which a set of front-end and back-end tools have been developed to allow the conversion of HDL code into HIF code and vice versa. HIFSuite allows designers to manipulate and integrate heterogeneous components implemented by using different hardware description languages (HDLs). Moreover, HIFSuite includes tools, which rely on HIF APIs, for manipulating HIF descriptions in order to support code abstraction/refinement and postrefinement verification.

UNIVERCM: The UNIversal VERsatile Computational Model for Heterogeneous System Integration

Designers are more and more forced to define innovative models and methodologies for managing integration of heterogeneous components and heterogeneous Chip Multiprocessors (CMPs) in modern embedded systems. In this context, component-based design seems the more promising approach, but it suffers from the lack of a widely adopted Model of Computation (MoC) able to capture component heterogeneity. This paper proposes univerCM, a new model of computation based on the Heterogeneous Intermediate Format (HIF) with the aim of supporting bottom-up design and system integration from a set of heterogeneous components. HW and SW components can be described by means of different languages and according to different MoCs, toward a uniform intermediate description based on a rigorous semantics. A mapping from univerCM to SystemC is proposed then to obtain a homogeneous description intended for fast simulation, that can be also used as starting point for CMP design flows. Experimental results show the effectiveness of univerCM in managing system heterogeneity.

HIFSuite: Tools for HDL code conversion and manipulation

HIFSuite ia a set of tools and application programming interfaces (APIs) that provide support for modeling and verification of HW/SW systems. The core of HIFSuite is the HDL Intermediate Format (HIF) language upon which a set of front-end and back-end tools have been developed to allow the conversion of HDL code into HIF code and vice versa. HIFSuite allows designers to manipulate and integrate heterogeneous components implemented by using different hardware description languages (HDLs). Moreover, HIFSuite includes tools, which rely on HIF APIs, for manipulating HIF descriptions in order to support code abstraction/refinement and post-refinement verification.

Moving from co-simulation to simulation for effective smart systems design

Design of smart systems needs to cover a wide variety of domains, ranging from analogue to digital, with power devices, micro-sensors and actuators, up to MEMS. This high level of heterogeneity makes design a very challenging task, as each domain is supported by specific languages, modeling formalisms and simulation frameworks. A major issue is furthermore posed by simulation, that heavily impacts the design and verification loop and that is very hard to be built in such an heterogeneous context. On the other hand, achieving efficient simulation would indeed make smart system design feasible with respect to budget constraints. This work provides a formalization of the typical abstraction levels and design domains of a smart system. This taxonomy allows to identify a precise role in the design flow for co-simulation and simulation scenarios. Moreover, a methodology is proposed to move from the co-simulated heterogeneity to a simulatable homogeneous representation in C++ of the entire smart system. The impact of heterogeneous or homogeneous models of computation is also examined. Experimental results prove the effectiveness of the proposed C++ generation for reaching high-speed simulation.

A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection.

Pulse oximetry is a noninvasive and continuous method for monitoring the blood oxygen saturation level. This paper presents the design and testing of a single-chip pulse oximeter fabricated in a 0.35 µm CMOS process. The chip includes photodiode, transimpedance amplifier, analogue band-pass filters, analogue-to-digital converters, digital signal processor and LED timing control. The experimentally measured AC and DC characteristics of individual circuits including the DC output voltage of the transimpedance amplifier, transimpedance gain of the transimpedance amplifier, and the central frequency and bandwidth of the analogue band-pass filters, show a good match (within 1%) with the circuit simulations. With modulated light source and integrated lock-in detection the sensor effectively suppresses the interference from ambient light and 1/f noise. In a breath hold and release experiment the single chip sensor demonstrates consistent and comparable performance to commercial pulse oximetry devices with a mean of 1.2% difference. The single-chip sensor enables a compact and robust design solution that offers a route towards wearable devices for health monitoring.

UNIVERCM: The UNIversal VERsatile computational model for heterogeneous embedded system design

Modern embedded systems require a tight integration among several heterogeneous components including both digital and analog HW, as well as HW-dependent SW. Moreover, they have a strict interaction with the surrounding physical environment. Traditional approaches for modeling such systems rely either on homogeneous top-down methodologies or on co-simulation frameworks. The former are generally based on a single model of computation. Thus, they do not easily allow to integrate existing components built by using different formalisms. The latter assemble heterogeneous components without providing a rigorous formal support, thus making integration and validation a very hard tasks. This paper proposes UNIVERCM, a formal computational model that allows to represent with a uniform syntax and a precise semantics heterogeneous systems composed of SW, analog and digital HW, as well as the environment they are embedded in. UNIVERCM is not intended to be explicitly used to describe a system, but rather to automatically convert into a uniform representation different descriptions written by using heterogeneous modeling languages.

Refinement of UML/MARTE models for the design of networked embedded systems

Network design in distributed embedded applications is a novel challenging task which requires 1) the extraction of communication requirements from application specification and 2) the choice of channels and protocols connecting physical nodes. These issues are faced in the paper by adopting UML/MARTE as specification front-end and repository of refined versions of the model obtained by both simulation and analytical exploration of the design space. The emphasis is on using standard UML/MARTE elements for the description of networked embedded systems to allow re-use, tool interoperability and documentation generation. The approach is explained on a case study related to building automation.

Network Fault Model for Dependability Assessment of Networked Embedded Systems

This paper presents a network-based fault model for dependability assessment of distributed applications built over networked embedded systems. This fault model represents global failures in terms of wrong behavior of packet-based asynchronous data transmissions. Packets are subject to different faults, i.e., drop, cut, bit errors, and duplication; these events can model either HW/SW failures of the networked embedded systems or problems in the channel among them. The paper describes 1) the proposed fault model in relation with existing ones, 2) its possible application scenarios, and 3) a SystemC tool for the simulation of both fault-free and faulty wireless sensor networks. Experimental results show the validity of the approach in the verification of communication protocols and its support to determine the optimal number of nodes in a wireless sensor network based on the IEEE 802.15.4 standard. Part of the software is available at http://sourceforge.net/projects/scnsl/.

A formal support for homogeneous simulation of heterogeneous embedded systems

In the context of component-based design, this paper proposes a framework, for managing embedded system heterogeneity, that enriches an interchange format, the Heterogeneous Intermediate Format (HIF), with the universal model of computation UNIVERCM. The framework supports bottom-up design, system integration, adaptation and reuse by allowing automatic translation of heterogeneous components, described by means of different languages and according to different MoCs, towards a uniform intermediate description based on a rigorous semantics. The goal of the paper is to show how traditional semantics aspects coming from HW description language models, analog models and embedded SW can be effectively captured by UNIVERCM to produce a homogeneous model from heterogeneous components.