Michele Lora

Moving from co-simulation to simulation for effective smart systems design

Design of smart systems needs to cover a wide variety of domains, ranging from analogue to digital, with power devices, micro-sensors and actuators, up to MEMS. This high level of heterogeneity makes design a very challenging task, as each domain is supported by specific languages, modeling formalisms and simulation frameworks. A major issue is furthermore posed by simulation, that heavily impacts the design and verification loop and that is very hard to be built in such an heterogeneous context. On the other hand, achieving efficient simulation would indeed make smart system design feasible with respect to budget constraints. This work provides a formalization of the typical abstraction levels and design domains of a smart system. This taxonomy allows to identify a precise role in the design flow for co-simulation and simulation scenarios. Moreover, a methodology is proposed to move from the co-simulated heterogeneity to a simulatable homogeneous representation in C++ of the entire smart system. The impact of heterogeneous or homogeneous models of computation is also examined. Experimental results prove the effectiveness of the proposed C++ generation for reaching high-speed simulation.

Conservative behavioural modelling in systemc-AMS

SystemC has recently been extended with the Analogue and Mixed Signal (AMS) library, with the ultimate goal of providing simulation support to analogue electronics and continuous time behaviours. SystemC-AMS allows modelling of systems that are either conservative and extremely low level or continuous time and behavioural, which is limited compared to other AMS HDLs. This work faces up this challenge, by extending SystemCAMS support to a new level of abstraction, called Analogue Behavioural Modelling (ABM), covering models that are both behavioural and conservative. This leads to a methodology that uses SystemC-AMS constructs in a novel way. Full automation of the methodology allows proof of its effectiveness both in terms of accuracy and simulation performance, and application of the overall approach to a complex industrial Micro Electro- Mechanical System (MEMS) case study. The effectiveness of the proposed approach is further highlighted in the context of virtual platforms for smart systems, as adopting a C++-based language for MEMS simulation reduces the simulation time by about 2x, thus enhancing the design and integration flow.

Multi-level modeling of wireless embedded systems

The design of wireless embedded systems needs their efficient and realistic simulation to verify that requirements are met. The reproduction of communication behavior is crucial to assess the performance of hardware and software components, e.g., dependability and energy consumption. This work presents and discusses different levels of abstraction for the simulation of the communication behavior. Each level addresses different aspects of the communication and allows to specify different kinds of detail; furthermore, it requires a specific modeling approach. Their use and the corresponding computational overhead is shown in the specific case of the Bluetooth standard. We also show that simulation results obtained at a low abstraction level can be used at a higher one to drive design choices.

Code generation alternatives to reduce heterogeneous embedded systems to homogeneity

The high level of heterogeneity of modern embedded systems forces designers to use different formalisms, thus making reuse and integration very difficult tasks. Reducing such an heterogeneity to a homogeneous implementation is a key solution to allow both simulation and validation of the system. This paper proposes two novel flows to gain a C++ and a SystemC-AMS homogeneous implementations of starting heterogeneous system. The approaches are compared w.r.t. state of the art techniques in terms of performance and accuracy through the application to a complex case study.

Time-Constraint-Aware Optimization of Assertions in Embedded Software

Technology shrinking and sensitization have led to more and more transient faults in embedded systems. Transient faults are intermittent and non-predictable faults caused by external events, such as energetic particles striking the circuits. These faults do not cause permanent damages, but may affect the running applications. One way to ensure the correct execution of these embedded applications is to keep debugging and testing even after shipping of the systems, complemented with recovery/restart options. In this context, the executable assertions that have been widely used in the development process for design validation can be deployed again in the final product. In this way, the application will use the assertion to monitor itself under the actual execution and will not allow erroneous out-of-the-specification behavior to manifest themselves. This kind of software-level fault tolerance may represent a viable solution to the problem of developing commercial off-the-shelf embedded systems with dependability requirements. But software-level fault tolerance comes at a computational cost, which may affect time-constrained applications. Thus, the executable assertions shall be introduced at the best possible points in the application code, in order to satisfy timing constraints, and to maximize the error detection efficiency. We present an approach for optimization of executable assertion placement in time-constrained embedded applications for the detection of transient faults. In this work, assertions have different characteristics such as tightness, i.e., error coverage, and performance degradation. Taking into account these properties, we have developed an optimization methodology, which identifies candidate locations for assertions and selects a set of optimal assertions with the highest tightness at the lowest performance degradation. The set of selected assertions is guaranteed to respect the real-time deadlines of the embedded application. Experimental results have shown the effectiveness of the proposed approach, which provides the designer with a flexible infrastructure for the analysis of time-constrained embedded applications and transient-fault-oriented executable assertions.

A unifying flow to ease smart systems integration

This paper proposes a meet-in-the-middle approach for the modeling and simulation of heterogeneous systems. The starting point is a set of heterogeneous models, developed by adopting the designers favorite design language and formalism. The methodology exploits automatic translation, abstraction and integration flows to generate a single homogeneous system-level description, that allows fast system simulation. The approach is supported by two novel design domain/abstraction level taxonomies, that generalize a state-of the art taxonomy to identify what characteristics would allow efficient system-level simulation, together with the transformations that must be applied to the starting model to achieve them. The advantage of the approach on system design and prototyping is particularly evident on any kind of highly heterogeneous systems, such as smart systems. The overall automatic flow has been implemented and applied to an open-source case study to measure the performance of each identified abstraction level, and the impact of the proposed methodology.

Hardware Synthesis from Software-Oriented UML Descriptions

This paper presents a methodology to produce synthesizable HW descriptions starting from UML State Machine based representations. This problem has already been widely addressed in the past. However, all the previously proposed approaches present a common characteristic: they restrict the expressiveness of the starting model. In particular, a common approach consists on the definition of ad-hoc UML profiles to adapt UML to the typical constructs of the classical hardware description languages. Thus, forcing the designer to use only a subset of the UML modeling language. This differentiates the initial UML model for SW and HW design, thus contradicting the main assumption of Model-Based design and avoiding code reuse. This paper aims at overcoming this limitation, by allowing the designer to use the same models for SW and HW design. To achieve this result, the UML description is mapped into a general purpose Model of Computation, called univer CM, to remove any ambiguity of the UML definition. After the application of some manipulations, the automata composing the univer CM models are translated into VHDL processes respecting the templates defined for the HW synthesis. The proposed approach has been validated on some commercial designs.

On the reuse of RTL assertions in SystemC TLM verification

Reuse of existing and already verified intellectual property (IP) models is a key strategy to cope with the complexity of designing modern system-on-chips (SoC)s under ever stringent time-to-market requirements. In particular, the recent trend towards system-level design and transaction level modeling (TLM) gives rise to new challenges for reusing existing RTL IPs and their verification environment in TLM-based design flows. While techniques and tools to abstract RTL IPs into TLM models have begun to appear, the problem of reusing, at TLM, a verification environment originally developed for an RTL IP is still underexplored, particularly when assertion-based verification (ABV) is adopted. Some techniques and frameworks have been proposed to deal with ABV at TLM, but they assume a top-down design and verification flow, where assertions are defined ex-novo at TLM level. In contrast, the reuse of existing assertions in an RTL-to-TLM bottom-up design flow has not been analyzed yet. This paper proposes a methodology to reuse assertions originally defined for a given RTL IP, to verify the corresponding TLM model. Experimental results have been conducted on benchmarks of different characteristics and complexity to show the applicability and the efficacy of the proposed methodology.

Virtual prototyping of smart systems through automatic abstraction and mixed-signal scheduling

Modern smart systems are usually built by implementing SW functionalities executed on HW platforms composed of both digital and analog components. Validation is mainly implemented through simulation of the functional behavior of the entire smart system modeled by a Virtual Platform. It is thus crucial to achieve fast mixed-signal simulation by removing unnecessary overhead due to synchronization between multiple tools and unimportant details. This work proposes a methodology to abstract mixed-signal systems, by integrating digital and analog components in a homogeneous virtual platform model for efficient simulation. Two main contributions are provided: 1) an automatic abstraction technique for analog components, allowing to preserve only the details meaningful for the functional behavior of the entire platform by moving complexity from simulation to generation time and 2) a novel scheduling technique that exploits temporal decoupling and synchronization of digital and analog processes, to simulate them together in a homogeneous model.

IP-XACT for smart systems design: extensions for the integration of functional and extra-functional models

Smart systems are miniaturized devices integrating computation, communication, sensing and actuation. As such, their design can not focus solely on functional behavior, but it must rather take into account different extra-functional concerns, such as power consumption or reliability. Any smart system can thus be modeled through a number of views, each focusing on a specific concern. Such views may exchange information, and they must thus be simulated simultaneously to reproduce mutual influence of the corresponding concerns. This paper shows how the IP-XACT standard, with some necessary extensions, can effectively support this simultaneous simulation. The extended IP-XACT descriptions allow to model extra-functional properties with a homogeneous format, defined by analysing requirements and characteristic of three main concerns, i.e., power, temperature and reliability. The IP-XACT descriptions are then used to automatically generate a skeleton of the simulation infrastructure in SystemC. The skeleton can be easily populated with models available in the literature, thus reaching simultaneous simulation of multiple concerns.