Francis Rivai

Nanoprobing on the SRAM static noise margin (SNM) soft fail analysis

As the semiconductor technology continues to scale, the stability and performance of embedded SRAM are growing concerns during the design and analysis stages. Maintaining an acceptable Static Noise Margin (SNM) in the embedded SRAM while scaling the minimum feature size and supply voltage of the integrated circuit (IC) becomes increasingly challenging. As a result, the manufacturing process window continues to shrink. This increases the difficulty for the failure analysis as many soft failures are induced by the reducing process margin. In this paper, a case study on an advanced technology node embedded SRAM soft fail was analyzed. Nanoprobing was employed at the room temperature to do SNM analysis at Metal 1 on the suspected location. Abnormal SNM window was observed at the room temperature analysis. Further analysis at high temperature on the same bit confirmed the soft failure bit. This correlates to the testing failure mode result. This case study is a good example for others who encounter same kind of the embedded SRAM soft failure.

Cross-sectional nanoprobing fault isolation technique on submicron devices

Abstract With continuous scaling on CMOS device dimensions, it is becoming increasingly challenging for conventional failure analysis (FA) methods to identify the failure mechanism at the circuit level in an integrated chip. Scanning Electron Microscopy (SEM) based nanoprobing is becoming an increasingly critical tool for identifying non-visual failures via electrical characterization in current electrical FA metrology for fault isolation since 2006 Toh et al. (2007), Shen et al. (2007), Ng et al. (2012) . Currently, most of the nanoprobing fault isolation is nanoprobe in top-down planar direction, such as nanoprobe on via, contact and metal line. This paper focused on fault isolation of sub-micron devices by nanoprobing on a cross-sectional plane. This is a new application area; it is very useful for sample that cannot perform fault isolation with conventional top-down planar nanoprobing, especially on non-volatile memory that with single transistor memory array that arrange in a vertical direction, such as Magnetic Random Access Memory (MRAM), Phase-Change Random Access Memory (PC-RAM), flash memory and etc.

Cross-sectional nanoprobing sample preparation on sub-micron device with fast laser grooving technique

Abstract Cross-sectional sample preparation is one of the most important failure analysis (FA) techniques in the semiconductor industry. It was commonly used for film stack critical dimension measurement, defect identification, electrical fault isolation and etc. However, cross-sectional sample preparation to a specific target location on a sub-micron device is very challenging and time-consuming. This is because of mechanical polishing easily caused metal smear, delamination, film peel-off, micro-cracked and etc. This paper focused on cross-sectional nanoprobing (XNP) sample preparation improvement in quality and quantity. A laser blast to deprocess or create a groove at near to target location before conventional mechanical polishing and focus ion beam (FIB) fine milling. The proposed technique not only reduces the sample preparation time to the sub-micron target location but also prevent mechanical damages that caused by mechanical polishing technique.

High temperature nanoprobing application for SRAM soft failure fault isolation

SRAM is a major component in semiconductor industry which often requires extensive and exhaustive method of fault isolation, especially for a non-visual defect in a soft failure mode. For these cases, nanoprobing on CA layer is often performed but there are times when it fails to isolate any defect. One reason may be because the failure only occurs at high temperature test environment. This paper will discuss the effectiveness of high temperature nanoprobing for SRAM soft failure fault isolation. 3 different case studies result from 3 similar SRAM devices which failed at high temperature test environment will be analyzed in this paper.

Fault isolation on the wafer with lithography hotspot signature

As the development of semiconductor process, more and more advanced technologies were applied in the IC manufacturing. The device becomes more precise, and more sensitive to the minor process variation. Failure analysis challenge comes along with these advanced processes. Lithography process is one of the most critical semiconductor processes. The issue with this process has its own property. Based on these properties the preliminary suspect can be made. This preliminary suspect will be helpful in the subsequent analysis. In this paper a failure mode with the hotspot wafer map pattern was submitted for analysis. The initial suspect is BEOL lithography process. Subsequently, EFA and PFA confirm the lithography related problem, but it is FEOL issue instead of BEOL. Combined with the process analysis, the mechanism was plotted.

Application of Scanning Capacitance Microscopy on SOI device with wafer edge low yield pattern

Abstract As semiconductor technology keeps scaling down, many advanced technology and process were applied in the semiconductor process. Especially for the application of IOT (internet of thing) technology, the low leakage and low power consumption product was the key component for this kind of application. SOI (Silicon-On-Insulator) wafer process is one of the advanced and important branches of the semiconductor manufacturing process. Its intrinsic advantage, low leakage and lower power consuming make it very suitable for personal communication device and IOT which match well with the application requirement. As is well known the SOI wafer is different form the normal bulk silicon wafer. The active sits on the silicon oxide insulator, which makes the final device separate from the substrate. Basically, all of the devices are floating on a nonconductive oxide layer. It comes with many challenges for process and analysis as compared with the conventional bulk silicon process. The most conventional analysis method is not applicable in the SOI device such as the PVC (passive voltage contrast) and current image methodology which are a very powerful and important in the failure analysis. In this paper, scanning capacitance is successfully used as the substitution of the PVC method. The SCM (Scanning Capacitance Microscopy) is a complicated process. Since all of the abnormality or physical change will affect the measured capacitance, then the capacitance signal will theoretically has many information with itself, including open, short and leakage. Through the detailed study, the contact level top-down SCM was successfully applied on the SOI unit. By proper setting of SCM bias condition, it can not only visualize the possible leaky location but also can reveal the possible path. Further nanoprobing and TEM (Transmission Electron Microscopy) have confirmed the SCM analysis.

Electrical analysis on implantation-related defect by nanoprobing methodology

Abstract Implantation is the key process in the modern semiconductor process which forms the basic device cell by different doping ditribution, depth, angle and element type. They are the key factors to affect the transistor performance, but the implantation-related defect is invisible by the normal failure analysis method. Then electrical analysis and verification is necessary to visualize this kind of defect. Electrical theory is important in this kind of failure analysis to indirectly proven the problematic process. The transistor body effect is a well know effect which is utilized in some kind of IC design to change the transistor Vth for certain purpose. But nobody uses this effect for the implantation-related failure analysis since the implant itself is complex and is not ideally uniform as the theory model. In this paper, implantation-related defect was successfully identified by the application of transistor body effect combined with nanoprobing on the localized structure.

Application of Fast Laser Deprocessing Techniques on large cross-sectional view area sample with FIB-SEM dual beam system

Abstract Cross-sectional analysis is one of the important areas for physical failure analysis. Focus Ion Beam (FIB) and mechanical polish sample preparation are commonly used and necessary techniques in the semiconductor industry and Failure Analysis (FA) Company (Wills and Perungulam, 2007). However, each technique has its own limitation. Mechanical polishing technique easily induces artifact by mechanical force, especially on advance technology node. FIB can eliminate mechanically damaged artifact, but have the limitation on cross-sectional view area. Another potential technique will be plasma FIB, it used very high milling current and fast milling speed (Hrnciř et al., 2013). However, it comes with a very high cost and having the contamination issue. The contamination issue greatly affects the low kV Scanning Electron Microscopy (SEM) imaging quality. In recent semiconductor industry FA, low kV SEM imaging is preferable, because high kV imaging will introduce delamination artifacts especially on organic material from packaged sample. In this paper, Fast Laser Deprocessing Techniques (FLDT) application is further enhanced on large area cross-sectional FA with fast cycle time and low-cost equipment. This is to prevent from mechanical damage. In short, the proposed FLDT is a cost-effective and quick way to deprocess a sample for defect identification in cross-sectional FA.