Zhihong Mai

Evidence of ultra-low-k dielectric material degradation and nanostructure alteration of the Cu/ultra-low-k interconnects in time-dependent dielectric breakdown failure

Ultra-low-k time-dependent dielectric breakdown (TDDB) is one of the most important reliability issues in Cu/low-k technology development due to its weaker intrinsic breakdown strength compared to SiO2 dielectrics. With continuous technology scaling, this problem is further exacerbated for Cu/ultra-low-k interconnects. In this letter, the TDDB degradation behavior of ultra-low-k dielectric in Cu/ultra-low-k interconnects will be investigated by a method consisting of a combination of Raman with Fourier transform infrared vibrational microscopes. In TDDB tests on Cu/low-k interconnect, it was found that intrinsic degradation of the ultra-low-k dielectric would first occur under electrical field stress. Upon further electrical field stress, the ultra-low-k dielectric degradation would be accelerated due to Ta ions migration from the Ta/TaN barrier bi-layer into the ultra-low-k dielectrics. In addition, no out-diffusion of Cu ions was observed in our investigation on Cu/Ta/TaN/SiCOH structures.

Vibrational spectroscopy of low-k/ultra-low-k dielectric materials on patterned wafers

Comparing with much valuable research on vibrational spectroscopy on low-k dielectrics in different substrates, this paper investigates the vibrational spectroscopy of low-k and ultra-low-k dielectric materials on patterned wafers. It is found that both Raman and FTIR spectroscopy are necessary as complement to characterize low-k and ultra-low-k dielectric materials on patterned wafers. Significant differences in the Raman and FTIR spectra between low-k and ultra-low-k dielectric materials are also observed. Moreover, Raman spectroscopy has an advantage in analyzing the mixed structure of low-k/ultra-low-k and Cu at nanometer-scaled sizes. The results in this paper show that Raman combined with FTIR spectroscopy is an effective tool to characterize dielectric thin film properties on patterned wafers.

Failure mechanism analysis and process improvement on time-dependent dielectric breakdown of Cu/ultra-low-k dielectric based on complementary Raman and FTIR spectroscopy study

Time-dependent dielectric breakdown (TDDB) is one of the most important reliability issues in Cu/low-k technology development. With continuous technology scaling to nanometer scale, TDDB issue is further exacerbated. In this paper, two failure mechanisms were investigated: the Ta ions migration model and the line-edge-roughness (LER) model, which is rendering the observed TDDB failure. Complimentary Raman and FTIR spectroscopy were applied to investigate the dielectric bonding characteristics. Our experimental results revealed the TDDB degradation behavior of Cu/ultra-low-k interconnects, suggesting the intrinsic degradation of the ultra-low-k dielectric. No out-diffusion of Cu ions was observed in Cu/Ta/TaN/SiCOH structures. Extensive TEM analysis further verified the migration of Ta ions from the Ta/TaN barrier bi-layer into the ultra-low-k dielectrics. Based on the LER model analysis, a comparative study in both passing and failing die elaborates that the slopped trench/via profile affected the TDDB performance.

Infrared radiation detector linear arrays of high Tc superconducting thin films

Abstract An 8-element infrared radiation detector array of YBCO superconducting thin films has been manufactured. The films were deposited by excimer laser scanning ablation and were patterned by ion beam milling. The photoresponse of the detector array employing the critical current-temperature relation were investigated in the range of 8–14 μm. The array has an uniform photoresponse and a flat photoresponse-operating temperature curve when it operates below Tc. The average normalized detectivity ( D ∗ ) of the array is 2.46 × 10 9 cm Hz 1 2 W −1 and the average noise equivalent power ( NEP ) is 1.822 × 10 −12 W Hz − 1 2 .

Effectiveness of frequency mapping on 28 nm device broken scan chain failures

Frequency mapping methodology is an effective diagnostic tool for detection of manufacturing defects in scan chains. It analyses reflected laser modulations from toggling scan cells to localize defective scan path or scan cell. In this paper, we demonstrate experimentally that the use of solid immersion lens technology to enhance signal and spatial resolution is not a prerequisite for this technique up till 28 nm technology node. We present case studies to show the effectiveness of frequency mapping for detecting systematic and random broken scan chain failures on a 28 nm technology node test chip. We achieved 81% success rate in this methodology.

Enhancement of Raman signals from low-k dielectrics with angle-resolved light scattering on nanostructure patterned Cu/low-k interconnects of IC devices

This letter reports the enhancement of Raman signals from low-k dielectric materials in the Cu/low-k interconnects of nanoscale integrated circuit (IC) devices. The Cu nanostructure pattern of the IC device acted as an active substrate for light scattering by the surface plasmon effect, enhancing the Raman signals observed from the low-k dielectric material of the device. The enhancement of the Raman signal of the low-k material was found to be strongly dependent on the incident angle of the incident laser light. A maximally enhanced Raman intensity was achieved when this angle was approximately 45° relative to the surface normal. Our findings are significant to the characterization of low-k materials and the monitoring of low-k reliability in leading edge semiconductor technologies with nanometer-scale structures.

Static fault localization of subtle metallization defects using near infrared photon emission microscopy

Abstract In this paper, two electroluminescence phenomena, which enabled the static electrical fault localization of subtle back-end-of-line metallization defects using near-infrared photon emission microscopy in the logic circuitry and the memory array, are described. In the logic circuitry, through the study of the defect-induced hot carrier emissions from the combinational logic gates, distinctive differences in emission characteristic between open and short defects are identified. Using this defect induced emission characterization approach, together with layout trace and analysis, the type of defect can be predicted. The defect physical location, which yielded no detectable hotspot signal, can also be narrowed down along the long failure net. This allows for the selection of the most appropriate physical failure analysis approach for defect viewing and thus achieving significant reduction in failure analysis cycle time. In the memory array, the weak emission from partially turned-on pass gate transistor is leveraged to localize marginal opens and shorts on the wordline node of the pass-gate transistor. These approaches are applied with great success in the foundry environment to localize yield limiting defects that resulted in SCAN and memory build-in self-test failure, without memory bitmap, diagnostic support or measurable IDD leakage, on advanced technology nodes devices. A discussion on the factors that influence the success rate of this approach is also provided.

Nanoprobing on the SRAM static noise margin (SNM) soft fail analysis

As the semiconductor technology continues to scale, the stability and performance of embedded SRAM are growing concerns during the design and analysis stages. Maintaining an acceptable Static Noise Margin (SNM) in the embedded SRAM while scaling the minimum feature size and supply voltage of the integrated circuit (IC) becomes increasingly challenging. As a result, the manufacturing process window continues to shrink. This increases the difficulty for the failure analysis as many soft failures are induced by the reducing process margin. In this paper, a case study on an advanced technology node embedded SRAM soft fail was analyzed. Nanoprobing was employed at the room temperature to do SNM analysis at Metal 1 on the suspected location. Abnormal SNM window was observed at the room temperature analysis. Further analysis at high temperature on the same bit confirmed the soft failure bit. This correlates to the testing failure mode result. This case study is a good example for others who encounter same kind of the embedded SRAM soft failure.

Electrical simulation on the localized NVM failed cell by AFP nanoproing

As semiconductor technology advance, NVM memory structure find more and more application in the IC product. Majority part of NVM is charge-based where charge can be injected into or removed from a critical region of a device. This storage cell is normally floating and cannot be accessed directly. So the analysis on this floating structure is quite challenge, especially on the specific cell of the prime die. In this paper, a kind of NVM structure, OTP, was analyzed by the AFP nanoprobing. Combined with layout physical structure analysis an d electrical simulation on the failed cell by AFP, the failure mechanism was built up. Based on the electrical and circuit analysis, physical analysis, TEM cut, on the specific location was performed. Physical defect was observed, and the electrical analysis was proven.

Top-down delayering to expose large inspection area on die side-edge with Platinum (Pt) deposition technique

Abstract The shrinking in feature sizes of semiconductor devices from integrated circuit (IC) 1 and function complexity has led to greater PFA 2 delayering challenges. The challenges stem from incorporation of top thick hard Silicon Dioxide (SiO 2 ) material that is formed from Tetra Ethyl Ortho Silicate (TEOS) 3 as Inter-Metal Dielectric (IMD) 4 and very thin ultra low-k dielectric material. For a device in copper (Cu) metal line technology, it is almost impossible to expose the entire layer at the same surface flatness by using a conventional top down polishing method, especially at the interface on TEOS and ultra low-k layer where dies side-edge is always thinner than die center (edging effect). Hence, for cases that required PFA delayering on the die side-edge especially for those packaged device or skeleton die, it is extremely challenging for PFA skillset. This paper outlines a proposed technique; perform Platinum (Pt) deposition on the selective area to slow down the side-edging effect. This proposed technique is easy and less skillset dependent to deprocess sample for defect identification analysis.