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Featured researches published by Pik Kee Tan.


Journal of Vacuum Science and Technology | 2015

Enhancement of Raman signals from low-k dielectrics with angle-resolved light scattering on nanostructure patterned Cu/low-k interconnects of IC devices

Maggie Yamin Huang; Bo Liu; Pik Kee Tan; Jeffrey Lam; Zhihong Mai

This letter reports the enhancement of Raman signals from low-k dielectric materials in the Cu/low-k interconnects of nanoscale integrated circuit (IC) devices. The Cu nanostructure pattern of the IC device acted as an active substrate for light scattering by the surface plasmon effect, enhancing the Raman signals observed from the low-k dielectric material of the device. The enhancement of the Raman signal of the low-k material was found to be strongly dependent on the incident angle of the incident laser light. A maximally enhanced Raman intensity was achieved when this angle was approximately 45° relative to the surface normal. Our findings are significant to the characterization of low-k materials and the monitoring of low-k reliability in leading edge semiconductor technologies with nanometer-scale structures.


international symposium on the physical and failure analysis of integrated circuits | 2016

Nanoprobing on the SRAM static noise margin (SNM) soft fail analysis

C. Q. Chen; P. T. Ng; Francis Rivai; Yin Zhe Ma; Pik Kee Tan; Hao Tan; Jeffery Lam; Zhihong Mai

As the semiconductor technology continues to scale, the stability and performance of embedded SRAM are growing concerns during the design and analysis stages. Maintaining an acceptable Static Noise Margin (SNM) in the embedded SRAM while scaling the minimum feature size and supply voltage of the integrated circuit (IC) becomes increasingly challenging. As a result, the manufacturing process window continues to shrink. This increases the difficulty for the failure analysis as many soft failures are induced by the reducing process margin. In this paper, a case study on an advanced technology node embedded SRAM soft fail was analyzed. Nanoprobing was employed at the room temperature to do SNM analysis at Metal 1 on the suspected location. Abnormal SNM window was observed at the room temperature analysis. Further analysis at high temperature on the same bit confirmed the soft failure bit. This correlates to the testing failure mode result. This case study is a good example for others who encounter same kind of the embedded SRAM soft failure.


Journal of Vacuum Science and Technology | 2014

Structural and composition investigations at delayered locations of low k integrated circuit device by gas-assisted focused ion beam

Dandan Wang; Pik Kee Tan; Maggie Yamin Huang; Jeffrey Lam; Zhihong Mai

The authors report a new delayering technique – gas-assisted focused ion beam (FIB) method and its effects on the top layer materials of integrated circuit (IC) device. It demonstrates a highly efficient failure analysis with investigations on the precise location. After removing the dielectric layers under the bombardment of an ion beam, the chemical composition of the top layer was altered with the reduced oxygen content. Further energy-dispersive x-ray spectroscopy and Fourier transform infrared analysis revealed that the oxygen reduction lead to appreciable silicon suboxide formation. Our findings with structural and composition alteration of dielectric layer after FIB delayering open up a new insight avenue for the failure analysis in IC devices.


Microelectronics Reliability | 2018

Failure analysis on 14 nm FinFET devices with ESD CDM failure

C. Shaalini; Pik Kee Tan; Y. Z. Zhao; Binghai Liu; Y.Z. Ma; A. Quah; Y.L. Pan; Hao Tan; Zhihong Mai

Abstract Electrostatic Discharge (ESD) is an important area for the semiconductor industry because ESD has an impact on production yield and product quality. ESD problems are increasing and have become challenging in the semiconductor industry because of the trends toward higher speed and shrinking in technology node. By continually shrinking the transistor with technology scaling, the process, circuit design, and failure analysis (FA) are getting more challenging. This paper is about FA on a 14 nm Fin-Field Effect Transistor (FinFET) device which has ESD failure after Charged Device Model (CDM) test. In most ESD failure FA, most of the time found Electrical Over Stress (EOS), the important is to understand which process layer or design causing the EOS. At the same time, this paper also discusses the difficulties faced, the FA technique used, the bottleneck of the 14 nm FinFET FA by old technology node FA equipment, and the FA findings. Finally, the ESD failure was identified with Scanning Transmission Electron Microscope (STEM)/Energy Dispersive Spectroscopy (EDS) analysis. The FA findings of the failure are related to the front end of line (FEOL), the metal gate of FinFET was fused with active, and the material in the metal gate was out-diffused.


Microelectronics Reliability | 2018

Cross-sectional nanoprobing sample preparation on sub-micron device with fast laser grooving technique

Pik Kee Tan; Y. Z. Zhao; Francis Rivai; Binghai Liu; Y.L. Pan; R. He; Hao Tan; Zhihong Mai

Abstract Cross-sectional sample preparation is one of the most important failure analysis (FA) techniques in the semiconductor industry. It was commonly used for film stack critical dimension measurement, defect identification, electrical fault isolation and etc. However, cross-sectional sample preparation to a specific target location on a sub-micron device is very challenging and time-consuming. This is because of mechanical polishing easily caused metal smear, delamination, film peel-off, micro-cracked and etc. This paper focused on cross-sectional nanoprobing (XNP) sample preparation improvement in quality and quantity. A laser blast to deprocess or create a groove at near to target location before conventional mechanical polishing and focus ion beam (FIB) fine milling. The proposed technique not only reduces the sample preparation time to the sub-micron target location but also prevent mechanical damages that caused by mechanical polishing technique.


international symposium on the physical and failure analysis of integrated circuits | 2017

Study of Si nanocrystal growth and characterization for Si nanocrystal embeded nonvolatile memory

Bo Liu; Maggie Yamin Huang; Pik Kee Tan; Zhen Song; Zhihong Mai; Jeffrey Lam

Si nanocrystal samples were fabricated by pulsed laser deposition method. Through changing the growth Ar gas pressure, the Si nanocrystal size and density can be controlled. Our works provided a possible way to fabricate Si nanocrystal embedded nonvolatile memory.


international symposium on the physical and failure analysis of integrated circuits | 2017

High temperature nanoprobing application for SRAM soft failure fault isolation

Francis Rivai; C. Q. Chen; P. T. Ng; Pik Kee Tan; Hao Tan; Yin Zhe Ma; Zhihong Mai; Jeffrey Lam

SRAM is a major component in semiconductor industry which often requires extensive and exhaustive method of fault isolation, especially for a non-visual defect in a soft failure mode. For these cases, nanoprobing on CA layer is often performed but there are times when it fails to isolate any defect. One reason may be because the failure only occurs at high temperature test environment. This paper will discuss the effectiveness of high temperature nanoprobing for SRAM soft failure fault isolation. 3 different case studies result from 3 similar SRAM devices which failed at high temperature test environment will be analyzed in this paper.


international symposium on the physical and failure analysis of integrated circuits | 2017

Mechanism of abnormal dual-peak profiles in large tilt-angle ion implantation studied by SRIM analysis

Lei Zhu; Pik Kee Tan; Dandan Wang; Yamin Huang; Jeffrey Lam; Zhi Hong Mai

Large-tilt angle (LTA) implantation has been employed in Si manufacturing processes in many applications, such as lightly-doped drain and Halo Implant. The depth profile of implant ions usually consists of only single peak at incident angle of zero degree with respect to the perpendicular of the silicon surface. However, an abnormal dual-peak profile was observed at LTA (>40 degree) for both boron and phosphorous. By using a Monte Carlo method (SRIM) to simulate the ion implant process, it was found that the projected range of the implant ions agrees with the formation of the first peak position which is shallower in depth. However, the cause for the second peak which corresponds to a depth much deeper in the Si substrate was unknown. During the simulation, it was also found that when the tilt angle was increased, the sputtering yields and Si displacements increased significantly, and this phenomenon indicated that during the LTA implantation, Si damage may not be negligible. The Si damage effect, which was due to either low Si density or transient Si displacement in the simulation, could have led to partial incident ions penetrating much deeper into the Si substrate and thus, caused the emergence of the second peak.


international symposium on the physical and failure analysis of integrated circuits | 2017

A controlled, mechanical method for MEMS decapsulation

Hao Tan; Efrat Moyal; Huei Hao Yap; Yu Zhe Zhao; R. He; Yin Zhe Ma; Bing Hai Liu; C. Q. Chen; Pik Kee Tan; Jeffrey Lam; Zhi Hong Mai

As the applications of micro electronic mechanical system (MEMS) are booming, more and more research and development activities are involved in the MEMS industry. For every new MEMS product with new functions, the manufacturing process will be tailored to cope with the changes. This requires reliability work to ensure the robustness of the new process. Thus, failure analysis plays an important role in the process development and the success rate for MEMS FA will be critical. In this paper, we will discuss a new decapsulation approach using a wedge diamond indenter based tool. It is a pure mechanical method and most of all, the whole process can be visually guided and monitored with the onboard optical vision system. The precision knob based operation is controllable, which makes the success rate very high by every user. We have successfully applied this method to our MEMS FA cases and this paper will detail our experiences.


international symposium on the physical and failure analysis of integrated circuits | 2017

Si nano-particle characterization by atomic force microscopy and electronic beam techniques

Hao Tan; Jie Zhu; Yu Zhe Zhao; R. He; Yin Zhe Ma; Bing Hai Liu; C. Q. Chen; Pik Kee Tan; Jeffrey Lam; Zhi Hong Mai

Although nano-particles have attracted extensive studies in material science and technology for decades, how to measure the particle size efficiently and conveniently still remains to be a problem unsolved. In this paper, Si nano-particles prepared by annealing a very thin amorphous Si layer were inspected by atomic force microscopy (AFM) as well as SEM and TEM e-beam techniques. Results extracted from AFM images are larger than those from e-beam imaging techniques mainly due to AFM probe tip convolution effect. In order to correct the AFM tip/probe induced topography convolutions, strategy and approaches were explored by constructing a suitable tip geometry model and then applied to the different scenarios when particle size is larger or close to the tip radius. The conclusions are consequently applied to the current study and the corrected AFM results are satisfying.

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