Francisco Colodro Ruiz

A Hardware Implementation of CNNs Based on Pulse Stream Techniques

Cellular Neural Networks (CNNs) represents a computational paradigm which has evolved to cover a very broad class of problems and applications. Different implementations of CNNs using digital and analog technologies can be found in the literature. In this paper, a new hardware implementation is proposed that uses Pulse Stream Techniques (PST). PST techniques allow the implementation of large arrays of CNNs with programmable synapses, combining the best of both, digital and analog worlds.

A Fully Stochastic Fuzzy Logic Controller

Regarding hardware implementation, stochastic logic represents a good compromise between digital and analogue designs. This paper presents a hardware implementation of fuzzy logic controllers using stochastic logic. Unlike previous implementations, in this approach, all the operations in the fuzzy controller, that is, membership function generation, the inference process, and defuzzification, are carried out by means of a stochastic coding of the internal signals and simple logic gates. This produces a controller with reduced hardware complexity when compared to conventional digital implementations, while maintaining a good accuracy of the results.

AFAN, a Tool for the Automatic Design of Fuzzy and Neural Controllers

In the recent years, the number of ASIC designs which include a fuzzy or neural controllers inside, has increased. The basic structure of these controllers is usually repeated; therefore, it seems reasonable to create a tool to automate the development of these controllers. This paper presents a software tool called AFAN, designed to generate fuzzy and neural controllers. AFAN accounts for resolution, speed and area consumption in order to select the architecture of the controller that best accommodates to a set of user specifications. The result is a file containing a VHDL code of a directly synthesizable fuzzy or neural controller. A set of examples is provided in order to show the solutions produced by AFAN with different specifications.

A Mixed Parallel-Sequential SHNN for Large Networks

This paper presents an architecture for the implementation of a large Stochastic Hopfield Neural Networks (SHNNs). The sequential SHNN, originally proposed in [1], takes a long time to convergence. On the other hand, the connection between chips limits to one hundred the number of neurons of the fully parallel SHNN proposed in [2]–[3]. A multichip approach proposed in this paper overcome both problems. The architecture, using a mixed parallel-sequential strategy, reduces the number of interconection lines to k while accelerates the convergence time of the network in [1] by a factor k. A partitioning problem is simulated to evaluate the behavior of the network.