J. Tombs

Low-voltage CMOS operational amplifiers with wide input-output swing based on a novel scheme

A scheme to achieve low-voltage wide-bandwidth operation of CMOS op amps with rail-to-rail input and output swing and constant gm is presented. It is based on a novel concept that uses a floating voltage controlled voltage source in the feedback path of the op amp in order to keep its input terminals close to one of the supply rails. Postlayout simulations on a 1.2 V rail-to-rail op amp with 13 MHz GB are presented which verify the proposed scheme.

Floating-gate-based tunable CMOS low-voltage linear transconductor and its application to HF g/sub m/-C filter design

This paper presents a new CMOS low-voltage linear transconductor for very high frequency. It uses multiple-input floating-gate transistors in each inverter of the differential structure transconductor presented by Nauta [1992]. The proposed transconductor operates under a constant low-voltage supply as low as 1.2 V, and its transconductance and output resistance are independently tunable, as shown by experimental measurements. This architecture is suitable for use in high-frequency continuous-time filters with programmable center frequency and quality factor. Simulation results of a 10.7-MHz and Q=40 g/sub m/-C filter operating with a voltage supply of 1.4 V and with rail-to rail input swing are presented.

Noninvasive Fault Classification, Robustness and Recovery Time Measurement in Microprocessor-Type Architectures Subjected to Radiation-Induced Errors

In critical digital designs such as aerospace or safety equipment, radiation-induced upset events (single-event effects or SEEs) can produce adverse effects, and therefore, the ability to compare the sensitivity of various proposed solutions is desirable. As custom-hardened microprocessor solutions can be very costly, the reliability of various commercial off-the-shelf (COTS) processors can be evaluated to see if there is a commercially available microprocessor or microprocessor-type intellectual property (IP) with adequate robustness for the specific application. Most existing approaches for the measurement of this robustness of the microprocessor involve diverting the program flow and timing to introduce the bit flips via interrupts and embedded handlers added to the application program. In this paper, a tool based on an emulation platform using Xilinx field programmable gate arrays (FPGAs) is described, which provides an environment and methodology for the evaluation of the sensitivity of microprocessor architectures, using dynamic runtime fault injection. A case study is presented, where the robustness of MicroBlaze and Leon3 microprocessors executing a simple signal processing task written in C language is evaluated and compared. A hardened version of the program, where the key variables are protected, has also been tested, and its contributions to system robustness have also been evaluated. In addition, this paper presents a further improvement in the developed tool that allows not only the measurement of microprocessor robustness but, in addition, the study and classification of single-event upset (SEU) effects and the exact measurement of the recovery time (the time that the microprocessor takes to self repair and recover the fault-free state). The measurement of this recovery time is important for real-time critical applications, where criticality depends on both data correctness and timing. To demonstrate the proposed improvements, a new software program that implements two different software hardening techniques (one for Data and another for Control Flow) has been made, and a study of the recovery times in some significant fault-injection cases has been performed over the Leon3 processor.

Selective Protection Analysis Using a SEU Emulator: Testing Protocol and Case Study Over the Leon2 Processor

VLSI circuits for space application must be protected by the insertion of massive redundancy. However, this increases silicon area and the production costs, therefore designers can often consider leaving some large, noncritical subcircuits unprotected. This paper presents how FT-UNSHADES, a nonintrusive tool for fault injection on emulated hardware, helps designers to select the proper level of protection in every subcircuit. Using FT-UNSHADES, a test procedure is proposed that provides: 1) information about the quality of the test vectors, 2) a proper estimation of the number of injected faults required to get confidence about the results of a fault injection campaign, and 3) information about the criticality of individual subcircuits by selective fault injection campaigns. In addition, FT-UNSHADES allows the insertion of multi-bit flips. This test procedure has been applied to three different, protected and unprotected, versions of the well-known Leon2 processor, and the results are discussed here.

A Unified Environment for Fault Injection at Any Design Level Based on Emulation

Sensitivity of electronic circuits to radiation effects is an increasing concern in modern designs. As technology scales down, Single Event Upsets (SEUs) are made more frequent and probable, affecting not only space applications, but also applications at earths surface, like automotive applications. Fault injection is a method widely used to evaluate the SEU sensitivity of digital circuits. Among the existing fault injection techniques, those based on FPGA emulation have proven to be the fastest ones. In this paper a unified emulation environment which combines two fault injection techniques based on FPGA emulation is proposed. The new emulation environment provides both, a high speed tool for quick fault detection, and a medium speed tool for in-depth analysis of SEUs propagation. The experiments presented here show that the two techniques can be successfully applied in a complementary manner.

On the design of tunable fault tolerant circuits on SRAM-based FPGAs for safety critical applications

Mission-critical applications such as space or avionics increasingly demand high fault tolerance capabilities of their electronic systems. Among the fault tolerance characteristics, the performance and costs of an electronic system remain the leader factors in the space and avionics market. In particular, when considering SRAM-based FPGAs, specific hardening techniques generally based on Triple Modular Redundancy need to be adopted in order to guarantee the desired fault tolerance degree. While effectively increasing the fault tolerance capability, these techniques introduce an important performance degradation and a dramatic area overhead, that results in higher design costs. In this paper, we propose an innovative design flow that allow the implementation of fault tolerance circuits in SRAM-based FPGA devices with different fault tolerance capability degrees. We introduce a new metric that allows a designer to precisely estimate and set the desired fault tolerance capabilities. Experimental analysis performed on a realistic industrial-type case study demonstrates the efficiency of our methodology.

A New Approach to Estimate the Effect of Single Event Transients in Complex Circuits

We describe an approach for analyzing single event transients (SETs) in complex digital circuits. The approach combines accuracy with efficiency: simulation is used for propagating the SET from the affected gate to flip-flops/latches, while hardware emulation is then used to study the resulting single or multiple-bit upset. To assess the capability of the proposed approach to deal with complex circuits, we analyzed the propagation of SETs in a microprocessor. In this paper, we analyzed the contribution to the error rate of different SETs pulse width, as well as the impact of the workload.

FT-UNSHADES-uP: A platform for the analysis and optimal hardening of embedded systems in radiation environments

Designing dependable systems is a systematic task where area, power and performance are competing constraints. In many applications, design restrictions do not permit the total hardening of a design, leaving some internal circuitry vulnerable to radiation effects. Hierarchical analysis is necessary to identify the relative importance and vulnerability of individual sub-circuits in a design so that selective hardening can be optimally applied. This paper describes the tool FT-UNSHADES-uP which provides an environment and methodology for the rapid dynamic hierarchical analysis of embedded based processor systems using runtime fault injection. A case study is presented, analyzing the effects of fault injection in the embedded RAM and internal registers of a MicroBlaze uP system. The results can be used for the optimal hardening of the FPGA or ASIC design.

Radiation Environment Emulation for VLSI Designs: A Low Cost Platform based on Xilinx FPGA's

As technology shrinks, critical industrial applications have to be designed with special care. VLSI circuits become more sensitive to ambient radiation: it affects to the internal structures, combinational or sequential elements. The effects, known as single event effects (SEEs), are modeled as spontaneous logical changes in a running netlist. They can be mitigated at netlist design level by means of inserting massive redundancy logic in the IC memory elements, as well as designing robust deadlock-free state machines. Current techniques for the analysis and verification of the protection logic for VLSI are inefficient and expensive, lacking either speed or analysis. This paper presents the FT- As technology shrinks, critical industrial applications have to be designed with special care. VLSI circuits become more sensitive to ambient radiation: it affects to the internal structures, combinational or sequential elements. The effects, known as single event effects (SEEs), are modeled as spontaneous logical changes in a running netlist. They can be mitigated at netlist design level by means of inserting massive redundancy logic in the IC memory elements, as well as designing robust deadlock-free state machines. Current techniques for the analysis and verification of the protection logic for VLSI are inefficient and expensive, lacking either speed or analysis. This paper presents the FT-UNSHADES system. This system is a low cost emulator focused on bit-flip insertion and SEE analysis at hardware speed, based on a Xilinx Virtex-II. Radiation tests are emulated in a highly controlled process, using a non-intrusive method. As a result the system can insert and analyse at least 80 K faults per hour in a system with 2 million test vectors.UNSHADES system. This system is a low cost emulator focused on bit-flip insertion and SEE analysis at hardware speed, based on a Xilinx Virtex-II. Radiation tests are emulated in a highly controlled process, using a non-intrusive method. As a result the system can insert and analyse at least 80 K faults per hour in a system with 2 million test vectors.

Microprocessor and FPGA interfaces for in-system co-debugging in field programmable hybrid systems

Abstract Modern trends in technology require efficient control and processing platforms based on connected software-hardware subsystems. Due to their complexity and size, algorithms implemented on these platforms are difficult to test and verify. When these types of solution are being designed, it is necessary to provide information of the internal values of registers and memories of both the software and hardware during the execution of the complete system. The final architecture of the targeted design and its debugging capabilities strongly depends on how the hybrid system is connected and clocked. This article discusses different architectural strategies that have been adopted for a hybrid hardware-software platform, built ready for debugging, and that uses components that can be easily found with a few special features. All the solutions have been implemented and evaluated using the UNSHADES-2 framework.