Francisco Fons

FPGA-based Personal Authentication Using Fingerprints

The current technological age demands the deployment of biometric security systems not only in those stringent and highly reliable fields (forensic, government, banking, etc.) but also in a wide range of daily use consumer applications (internet access, border control, health monitoring, mobile phones, laptops, etc.) accessible worldwide to any user. In order to succeed in the exploitation of biometric applications over the world, it is needed to make research on power-efficient and cost-effective computational platforms able to deal with those demanding image and signal operations carried out in the biometric processing. The present work deals with the evaluation of alternative system architectures to those existing PC (personal computers), HPC (high-performance computing) or GPU-based (graphics processing unit) platforms in one specific scenario: the physical implementation of an AFAS (automatic fingerprint-based authentication system) application. The development of automated fingerprint-based personal recognition systems in the way of compute-intensive and real-time embedded systems under SoPC (system-on-programmable-chip) devices featuring one general-purpose MPU (microprocessor unit) and one run-time reconfigurable FPGA (field programmable gate array) proves to be an efficient and cost-effective solution. The provided flexibility, not only in terms of software but also in terms of hardware thanks to the programmability and run-time reconfigurability performance exhibited by the suggested FPGA device, permits to build any application by means of hardware-software co-design techniques. The parallelism and acceleration performances inherent to the hardware design and the ability of reusing hardware resources along the application execution time are key factors to improve the performance of existing systems.

Design of an Embedded Fingerprint Matcher System

The current technological age is demanding reliable and cost-effective personal authentication systems for a wide range of daily use applications such as access control, electronic commerce, ID verification... where security and confidentiality performance of the information is needed. Biometrics-based authentication techniques (e.g. face, iris, fingerprint recognition...) in conjunction with embedded systems technologies bring a challenging solution to this need. This paper describes the hardware-software co-design of a computational platform responsible for matching two fingerprint minutiae sets. A novel system concept is suggested by making use of reconfigurable architectures

Approaching Fingerprint Image Enhancement through Reconfigurable Hardware Accelerators

In this paper, an efficient hardware-software architecture is proposed to cope with the implementation of an automatic fingerprint recognition system. A flexible field programmable gate array (FPGA) device lets develop the image processing application so that the same logic substrate is reconfigured and reused by several custom coprocessors during the different operation stages of the sequential biometric algorithm. The results reached with this technology reveal that a middle-range reconfigurable FPGA faces both real-time and parallel compute-intensive demands of the fingerprint image enhancement process.

Flexible hardware for fingerprint Image Processing

Reconfigurable computing adds to the traditional hardware/software design flow a new degree of freedom in the development of electronic systems. In a system-on-chip platform, the fact that a MCU makes evolve at run-time a hardware coprocessor mapped on a FPGA, to execute thus different compute-intensive tasks in the same silicon-area, results in a clear earned value applied to the system implementation: the low-cost reached through the resources time-multiplexing. Under that approach, this work merges both reconfigurable computing and HW/SW co-design technologies to develop an efficient architecture of an automatic fingerprint authentication system (AFAS) oriented to real-time embedded applications.

Hardware-Software Co-design of a Fingerprint Matcher on Card

Nowadays, security is becoming a real need for society and a real challenge for those everyday activities such as access control, cash terminals, public transport, Internet... where user authentication is required prior to giving access to confidential information, relevant places or restricted resources. The implementation of a reliable personal recognition system not based on vulnerable topics such as physical keys or passwords is required. Biometrics-based authentication techniques (e.g. face, iris, fingerprint recognition...) in conjunction with smart cards technologies bring a challenging solution to this need. This paper describes the hardware-software co-design of a fingerprint match on card system responsible for matching two fingerprint minutiae sets in a reliable and secure way. The proposed system architecture is composed by a general-purpose 8-bit microcontroller and a 40-kgates FPGA, all embedded in a system on chip device. A good solution is detailed from a performance versus cost point-of-view

FPGA Implementation of the Ridge Line Following Fingerprint Algorithm

Most biometrics systems are implemented on high performance microprocessors executing complex algorithms on software. In order to develop a low-cost and high-speed coprocessor, floating-point computations have been substituted by fixed-point ones, and a pipeline scheme has been developed.

Design of FPGA-based Hardware Accelerators for On-line Fingerprint Matcher Systems

Nowadays fingerprints are the most widely used biometric characteristics in automatic personal authentication or identification systems. Most human recognition systems use those fingertip discontinuities called minutiae and mainly based on the ridge endings and the ridge bifurcations of the skin to perform fingerprint matching. A fingerprint pattern is thus defined by the spatial distribution of its distinctive traits. Matching two fingerprints in minutiae-based representations becomes a point pattern matching, and it consists of finding the alignment and correspondences between pairs of minutia points in both sets. Several algorithms have been proposed in the last decades to efficiently match two fingerprint minutiae sets. This paper describes the design of FPGA-based accelerators responsible for performing those computationally expensive tasks needed in the fingerprint matching process. The acceleration results obtained when partitioning the application in hardware and software tasks permits to make the conventional purely software-oriented and off-line matching algorithms suitable for on-line applications

Deployment of Run-Time Reconfigurable Hardware Coprocessors Into Compute-Intensive Embedded Applications

Day after day, embedded systems add more compute-intensive applications inside their end products: cryptography or image and video processing are some examples found in leading markets like consumer electronics and automotive. To face up these ever-increasing computational demands, the use of hardware accelerators synthesized in field-programmable gate arrays (FPGA) lets achieve processing speedups of orders of magnitude versus their counterpart CPU-based software approaches. However, the inherent increment in physical resources penalizes in cost. To address this issue, dynamically reconfigurable hardware technology definitively reached its maturity. SRAM-based reconfigurable logic goes beyond the classical conception of static hardware resources distributed in space and held invariant for the entire application life cycle; it provides a new design abstraction featured by the temporal partitioning of such resources to promote their continuous reuse, reconfiguring them on the fly to play a different role in each instant. This new computing paradigm lets balance the design of embedded applications by partitioning their functionality in space and time—through a series of mutually-exclusive processing tasks synthesized multiplexed in time on the same set of resources—and achieving thus cost savings in both area and power metrics. However, the exploitation of this system versatility requires special attention to avoid performance degradation. Such technical aspects are addressed in this work intended to be a survey on reconfigurable hardware technology and aimed at defining an open, standard and cost-effective system architecture driven by flexible coprocessors instantiated on demand on reconfigurable resources of an FPGA. This concept fits well with the functional features demanded to many embedded applications today and its feasibility has been proved with a state-of-the-art commercial SRAM-based FPGA platform. The achieved results highlight dynamic partial reconfiguration as a potential technology to lead the next computing wave in the industry.

Design of a Hardware Accelerator for Fingerprint Alignment

The uniqueness of human fingerprints has been accepted by the scientific community since long time ago. Proof of this is the fact that, among all physiological characteristics, fingerprints are the oldest and most deeply used signs of identity for personal recognition. However up to date, the development of an automatic fingerprint-based human authentication system is an open research problem. Most of the difficulties rely on the complexity and the high computational power needed to develop a fingerprint matching algorithm reliable enough to guarantee the accuracy of the result even when only low-quality fingerprint impressions are available from the users. In order to deal with the processing power requested by the system, an application-specific hardware accelerator developed by means of hardware-software co-design techniques is suggested in this work for the fingerprint alignment stage. The hardware processor permits to speed up the alignment phase and to reach real-time performance, which is not guaranteed when developing the same algorithm under a purely-software platform.

Embedded security: New trends in personal recognition systems

Nowadays biometrics and embedded systems technologies bring the required means to face those security challenges in the current technological age. The electronic age points to the embedded security as one efficient solution for those applications where confidential treatment of the information is needed. Moreover, the genuine biometric characteristics of each individual become the most reliable features to be used as personal identifiers in front of the world, replacing those low-security tokens such as ID cards, PINs and passwords. Following this direction, the HW-SW co-design of a fingerprint-based personal recognition system embedded on a dynamically reconfigurable platform is suggested in this work. The selected system architecture provides the power to design these high performance applications at low cost.