Enrique Cantó

Hardware-software co-design of an iris recognition algorithm

This paper describes the implementation of an iris recognition algorithm based on hardware-software co-design. The system architecture consists of a general-purpose 32- bit microprocessor and several slave coprocessors that accelerate the most intensive calculations. The whole iris recognition algorithm has been implemented on a low-cost Spartan 3 FPGA, achieving significant reduction in execution time when compared to a conventional software-based application. Experimental results show that with a clock speed of 40 MHz, an IrisCode is obtained in less than 523 ms from an image of 640x480 pixels, which is just 20% of the total time needed by a software solution running on the same microprocessor embedded in the architecture.

FPGA-based Personal Authentication Using Fingerprints

The current technological age demands the deployment of biometric security systems not only in those stringent and highly reliable fields (forensic, government, banking, etc.) but also in a wide range of daily use consumer applications (internet access, border control, health monitoring, mobile phones, laptops, etc.) accessible worldwide to any user. In order to succeed in the exploitation of biometric applications over the world, it is needed to make research on power-efficient and cost-effective computational platforms able to deal with those demanding image and signal operations carried out in the biometric processing. The present work deals with the evaluation of alternative system architectures to those existing PC (personal computers), HPC (high-performance computing) or GPU-based (graphics processing unit) platforms in one specific scenario: the physical implementation of an AFAS (automatic fingerprint-based authentication system) application. The development of automated fingerprint-based personal recognition systems in the way of compute-intensive and real-time embedded systems under SoPC (system-on-programmable-chip) devices featuring one general-purpose MPU (microprocessor unit) and one run-time reconfigurable FPGA (field programmable gate array) proves to be an efficient and cost-effective solution. The provided flexibility, not only in terms of software but also in terms of hardware thanks to the programmability and run-time reconfigurability performance exhibited by the suggested FPGA device, permits to build any application by means of hardware-software co-design techniques. The parallelism and acceleration performances inherent to the hardware design and the ability of reusing hardware resources along the application execution time are key factors to improve the performance of existing systems.

FPGA implementation of a minutiae extraction fingerprint algorithm

Fingerprint recognition is one of the most common techniques used for biometric identification. Currently fingerprint technology is suitable to recognize users with high accuracy and low execution times using microprocessors able to solve algorithms with high-computational cost. However, the microprocessorpsilas cost could make the use of fingerprint biometric conditional on specific applications. This paper presents the implementation of a whole minutiae extraction fingerprint algorithm using a Spartan-3 FPGA, as an appropriate solution for portable devices and for the low-cost consumer market. The internal architecture of the proposed embedded system is based on a soft-core microprocessor and several dedicated coprocessors designed in order to accelerate the resolution of the algorithm. Experimental results show as minutiae of fingerprint are obtained in 988 ms when an image of 256 times 256 pixels is analyzed.

Design of an Embedded Fingerprint Matcher System

The current technological age is demanding reliable and cost-effective personal authentication systems for a wide range of daily use applications such as access control, electronic commerce, ID verification... where security and confidentiality performance of the information is needed. Biometrics-based authentication techniques (e.g. face, iris, fingerprint recognition...) in conjunction with embedded systems technologies bring a challenging solution to this need. This paper describes the hardware-software co-design of a computational platform responsible for matching two fingerprint minutiae sets. A novel system concept is suggested by making use of reconfigurable architectures

A temporal bipartitioning algorithm for dynamically reconfigurable FPGAs

This paper will describe a systematic method to map synchronous digital systems into dynamically reconfigurable programmable logic (i.e., programmable logic able to swap in real time the configuration defining the functionality of the system). The method is based on a temporal bipartitioning technique that is able to separate the static implementation of a circuit in two temporal independence hardware contexts. As the experimental results show, the method is capable of improving the functional density of the dynamic implementation with respect to the static one.

Feasible Evolutionary and Self-Repairing Hardware by Means of the Dynamic Reconfiguration Capabilities of the FIPSOC Devices

In this paper we shall address the paradigms of evolutionary and self-repairing hardware using a new family of programmable devices, called FIPSOC (Field Programmable System On a Chip). The most salient feature of these devices is the integration on a single chip of a programmable digital section, a programmable analog section and a general-purpose microcontroller. Furthermore, the programmable digital section has been designed including a flexible and fast dynamic reconfiguration scheme. These properties provide an efficient framework for tackling the specific features posed by the emerging field of evolutionary computation. We shall demonstrate this fact by means of two different case studies: a self-repairing strategy for digital systems, suitable for applications in environments exposed to radiation, and an efficient implementation scheme for evolving parallel cellular machines.

Approaching Fingerprint Image Enhancement through Reconfigurable Hardware Accelerators

In this paper, an efficient hardware-software architecture is proposed to cope with the implementation of an automatic fingerprint recognition system. A flexible field programmable gate array (FPGA) device lets develop the image processing application so that the same logic substrate is reconfigured and reused by several custom coprocessors during the different operation stages of the sequential biometric algorithm. The results reached with this technology reveal that a middle-range reconfigurable FPGA faces both real-time and parallel compute-intensive demands of the fingerprint image enhancement process.

Flexible hardware for fingerprint Image Processing

Reconfigurable computing adds to the traditional hardware/software design flow a new degree of freedom in the development of electronic systems. In a system-on-chip platform, the fact that a MCU makes evolve at run-time a hardware coprocessor mapped on a FPGA, to execute thus different compute-intensive tasks in the same silicon-area, results in a clear earned value applied to the system implementation: the low-cost reached through the resources time-multiplexing. Under that approach, this work merges both reconfigurable computing and HW/SW co-design technologies to develop an efficient architecture of an automatic fingerprint authentication system (AFAS) oriented to real-time embedded applications.

Reconfigurable OPB Coprocessors for a Microblaze Self-Reconfigurable SOC Mapped on Spartan-3 FPGAs

Dynamically reconfigurable FPGAs are usually based on internal SRAM configuration memory, that can be fully or partially written from an external device. One of their applications is to map reconfigurable coprocessors, so an external microprocessor can change during run-time the coprocessor mapped on a FPGA. Coprocessors can execute the time-critical tasks of an algorithm, while the general purpose microprocessor executes the rest of computations and controls the FPGA reconfiguration. Microblaze is a soft-core 32-bit microprocessor designed to be implemented as a part of a system-on-chip (SOC) mapped on Xilinx FPGAs. The Xilinx EDK software allows designers to map a SOC composed of a Microblaze plus several OPB (on-chip peripheral bus) peripherals. But the EDK was not designed to allow reconfigurable OPB peripherals mapped on the FPGA device. This paper demonstrates that it is possible to design an self-reconfigurable SOC mapped on a low-cost Spartan-3 FPGA, where an area section is devoted to map several reconfigurable OPB coprocessors in a time-multiplexed way

Hardware-Software Co-design of a Fingerprint Matcher on Card

Nowadays, security is becoming a real need for society and a real challenge for those everyday activities such as access control, cash terminals, public transport, Internet... where user authentication is required prior to giving access to confidential information, relevant places or restricted resources. The implementation of a reliable personal recognition system not based on vulnerable topics such as physical keys or passwords is required. Biometrics-based authentication techniques (e.g. face, iris, fingerprint recognition...) in conjunction with smart cards technologies bring a challenging solution to this need. This paper describes the hardware-software co-design of a fingerprint match on card system responsible for matching two fingerprint minutiae sets in a reliable and secure way. The proposed system architecture is composed by a general-purpose 8-bit microcontroller and a 40-kgates FPGA, all embedded in a system on chip device. A good solution is detailed from a performance versus cost point-of-view