Mariano López

Building a chemical ontology using Methontology and the Ontology Design Environment

Methontology provides guidelines for specifying ontologies at the knowledge level, as a specification of a conceptualization. ODE enables ontology construction, covering the entire life cycle and automatically implementing ontologies. To meet the challenge of building ontologies, we have developed Methontology, a framework for specifying ontologies at the knowledge level, and the Ontology Development Environment. We present our experience in using Methontology and ODE to build the chemical ontology.

Hardware-software co-design of an iris recognition algorithm

This paper describes the implementation of an iris recognition algorithm based non hardware-software co-design. The system architecture consists of a general-purpose 32- nbit microprocessor and several slave coprocessors that accelerate the most intensive ncalculations. The whole iris recognition algorithm has been implemented on a low-cost nSpartan 3 FPGA, achieving significant reduction in execution time when compared to a nconventional software-based application. Experimental results show that with a clock nspeed of 40 MHz, an IrisCode is obtained in less than 523 ms from an image of 640x480 npixels, which is just 20% of the total time needed by a software solution running on the nsame microprocessor embedded in the architecture.

Ontology's Crossed Life Cycles

This paper presents the idea that the life cycle of an ontology is highly impacted as a result of the process of reusing it for building another ontology. One of the more important results of the experiment presented is how the different activities to be carried out during the development of a specific ontology may involve performing other types of activities on other ontologies already built or under construction. We identify in that paper new intra-dependencies between activities carried out inside the same otology and interdependencies between activities carried out in different ontologies. The interrelation between life cycles of several ontologies provokes that integration has to be approached globally rather than as a mere integration of out implementation.

FPGA-based Personal Authentication Using Fingerprints

The current technological age demands the deployment of biometric security systems not only in those stringent and highly reliable fields (forensic, government, banking, etc.) but also in a wide range of daily use consumer applications (internet access, border control, health monitoring, mobile phones, laptops, etc.) accessible worldwide to any user. In order to succeed in the exploitation of biometric applications over the world, it is needed to make research on power-efficient and cost-effective computational platforms able to deal with those demanding image and signal operations carried out in the biometric processing. The present work deals with the evaluation of alternative system architectures to those existing PC (personal computers), HPC (high-performance computing) or GPU-based (graphics processing unit) platforms in one specific scenario: the physical implementation of an AFAS (automatic fingerprint-based authentication system) application. The development of automated fingerprint-based personal recognition systems in the way of compute-intensive and real-time embedded systems under SoPC (system-on-programmable-chip) devices featuring one general-purpose MPU (microprocessor unit) and one run-time reconfigurable FPGA (field programmable gate array) proves to be an efficient and cost-effective solution. The provided flexibility, not only in terms of software but also in terms of hardware thanks to the programmability and run-time reconfigurability performance exhibited by the suggested FPGA device, permits to build any application by means of hardware-software co-design techniques. The parallelism and acceleration performances inherent to the hardware design and the ability of reusing hardware resources along the application execution time are key factors to improve the performance of existing systems.

FPGA implementation of a minutiae extraction fingerprint algorithm

Fingerprint recognition is one of the most common techniques used for biometric identification. Currently fingerprint technology is suitable to recognize users with high accuracy and low execution times using microprocessors able to solve algorithms with high-computational cost. However, the microprocessorpsilas cost could make the use of fingerprint biometric conditional on specific applications. This paper presents the implementation of a whole minutiae extraction fingerprint algorithm using a Spartan-3 FPGA, as an appropriate solution for portable devices and for the low-cost consumer market. The internal architecture of the proposed embedded system is based on a soft-core microprocessor and several dedicated coprocessors designed in order to accelerate the resolution of the algorithm. Experimental results show as minutiae of fingerprint are obtained in 988 ms when an image of 256 times 256 pixels is analyzed.

Real-time embedded systems powered by FPGA dynamic partial self-reconfiguration: a case study oriented to biometric recognition applications

This work aims to pave the way for an efficient open system architecture applied to embedded electronic applications to manage the processing of computationally complex algorithms at real-time and low-cost. The target is to define a standard architecture able to enhance the performance-cost trade-off delivered by other alternatives nowadays in the market like general-purpose multi-core processors. Our approach, sustained by hardware/software (HW/SW) co-design and run-time reconfigurable computing, is synthesizable in SRAM-based programmable logic. As proof-of-concept, a run-time partially reconfigurable field-programmable gate array (FPGA) is addressed to carry out a specific application of high-demanding computational power such as an automatic fingerprint authentication system (AFAS). Biometric personal recognition is a good example of compute-intensive algorithm composed of a series of image processing tasks executed in a sequential order. In our pioneer conception, these tasks are partitioned and synthesized first in a series of coprocessors that are then instantiated and executed multiplexed in time on a partially reconfigurable region of the FPGA. The implementation benchmark of the AFAS either as a pure software approach on a PC platform under a dual-core processor (Intel Core 2 Duo T5600 at 1.83xa0GHz) or as a reconfigurable FPGA co-design (identical algorithm partitioned in HW/SW tasks operating at 50 or 100xa0MHz on the second smallest device of the Xilinx Virtex-4 LX family) highlights a speed-up of one order of magnitude in favor of the FPGA alternative. These results let point out biometric recognition as a sensible killer application for run-time reconfigurable computing, mainly in terms of efficiently balancing computational power, functional flexibility and cost. Such features, reached through partial reconfiguration, are easily portable today to a broad range of embedded applications with identical system architecture.

Flexible hardware for fingerprint Image Processing

Reconfigurable computing adds to the traditional hardware/software design flow a new degree of freedom in the development of electronic systems. In a system-on-chip platform, the fact that a MCU makes evolve at run-time a hardware coprocessor mapped on a FPGA, to execute thus different compute-intensive tasks in the same silicon-area, results in a clear earned value applied to the system implementation: the low-cost reached through the resources time-multiplexing. Under that approach, this work merges both reconfigurable computing and HW/SW co-design technologies to develop an efficient architecture of an automatic fingerprint authentication system (AFAS) oriented to real-time embedded applications.

Reconfigurable OPB Coprocessors for a Microblaze Self-Reconfigurable SOC Mapped on Spartan-3 FPGAs

Dynamically reconfigurable FPGAs are usually based on internal SRAM configuration memory, that can be fully or partially written from an external device. One of their applications is to map reconfigurable coprocessors, so an external microprocessor can change during run-time the coprocessor mapped on a FPGA. Coprocessors can execute the time-critical tasks of an algorithm, while the general purpose microprocessor executes the rest of computations and controls the FPGA reconfiguration. Microblaze is a soft-core 32-bit microprocessor designed to be implemented as a part of a system-on-chip (SOC) mapped on Xilinx FPGAs. The Xilinx EDK software allows designers to map a SOC composed of a Microblaze plus several OPB (on-chip peripheral bus) peripherals. But the EDK was not designed to allow reconfigurable OPB peripherals mapped on the FPGA device. This paper demonstrates that it is possible to design an self-reconfigurable SOC mapped on a low-cost Spartan-3 FPGA, where an area section is devoted to map several reconfigurable OPB coprocessors in a time-multiplexed way

Hardware-software co-design of an automatic fingerprint acquisition system

Nature has provided human beings unique and different each one in relation to the others; even identical twins have infinite differences between them. Every individual has his own biological characteristics that allow him to be distinguished from the rest of the humanity. In recent years, biometrics and computer technology have joined together in order to improve the security in everyday activities such as access control systems, cash terminals, public transport, internet, smart card readers... where user identification/authentication is required before giving him access to confidential information, relevant places or restricted resources. In any situation where rapid, accurate, reliable and secure identification or authentication of an individual is required, electronics and biometrics take place. With biometrics-based security systems there is no longer any need to remember a large number of PINs and passwords, so the genuine biometric characteristics of every individual play the role of personal identity code in front of the world. The first stage in these identification systems is the biometric characteristic acquisition. The authors focus their work on that field in the specific case of using fingerprints as biometric feature. A good solution is detailed from a performance vs cost point-of-view.

Hardware-Software Co-design of a Fingerprint Matcher on Card

Nowadays, security is becoming a real need for society and a real challenge for those everyday activities such as access control, cash terminals, public transport, Internet... where user authentication is required prior to giving access to confidential information, relevant places or restricted resources. The implementation of a reliable personal recognition system not based on vulnerable topics such as physical keys or passwords is required. Biometrics-based authentication techniques (e.g. face, iris, fingerprint recognition...) in conjunction with smart cards technologies bring a challenging solution to this need. This paper describes the hardware-software co-design of a fingerprint match on card system responsible for matching two fingerprint minutiae sets in a reliable and secure way. The proposed system architecture is composed by a general-purpose 8-bit microcontroller and a 40-kgates FPGA, all embedded in a system on chip device. A good solution is detailed from a performance versus cost point-of-view