Mariano Fons

FPGA-based Personal Authentication Using Fingerprints

The current technological age demands the deployment of biometric security systems not only in those stringent and highly reliable fields (forensic, government, banking, etc.) but also in a wide range of daily use consumer applications (internet access, border control, health monitoring, mobile phones, laptops, etc.) accessible worldwide to any user. In order to succeed in the exploitation of biometric applications over the world, it is needed to make research on power-efficient and cost-effective computational platforms able to deal with those demanding image and signal operations carried out in the biometric processing. The present work deals with the evaluation of alternative system architectures to those existing PC (personal computers), HPC (high-performance computing) or GPU-based (graphics processing unit) platforms in one specific scenario: the physical implementation of an AFAS (automatic fingerprint-based authentication system) application. The development of automated fingerprint-based personal recognition systems in the way of compute-intensive and real-time embedded systems under SoPC (system-on-programmable-chip) devices featuring one general-purpose MPU (microprocessor unit) and one run-time reconfigurable FPGA (field programmable gate array) proves to be an efficient and cost-effective solution. The provided flexibility, not only in terms of software but also in terms of hardware thanks to the programmability and run-time reconfigurability performance exhibited by the suggested FPGA device, permits to build any application by means of hardware-software co-design techniques. The parallelism and acceleration performances inherent to the hardware design and the ability of reusing hardware resources along the application execution time are key factors to improve the performance of existing systems.

Design of an Embedded Fingerprint Matcher System

The current technological age is demanding reliable and cost-effective personal authentication systems for a wide range of daily use applications such as access control, electronic commerce, ID verification... where security and confidentiality performance of the information is needed. Biometrics-based authentication techniques (e.g. face, iris, fingerprint recognition...) in conjunction with embedded systems technologies bring a challenging solution to this need. This paper describes the hardware-software co-design of a computational platform responsible for matching two fingerprint minutiae sets. A novel system concept is suggested by making use of reconfigurable architectures

Approaching Fingerprint Image Enhancement through Reconfigurable Hardware Accelerators

In this paper, an efficient hardware-software architecture is proposed to cope with the implementation of an automatic fingerprint recognition system. A flexible field programmable gate array (FPGA) device lets develop the image processing application so that the same logic substrate is reconfigured and reused by several custom coprocessors during the different operation stages of the sequential biometric algorithm. The results reached with this technology reveal that a middle-range reconfigurable FPGA faces both real-time and parallel compute-intensive demands of the fingerprint image enhancement process.

Flexible hardware for fingerprint Image Processing

Reconfigurable computing adds to the traditional hardware/software design flow a new degree of freedom in the development of electronic systems. In a system-on-chip platform, the fact that a MCU makes evolve at run-time a hardware coprocessor mapped on a FPGA, to execute thus different compute-intensive tasks in the same silicon-area, results in a clear earned value applied to the system implementation: the low-cost reached through the resources time-multiplexing. Under that approach, this work merges both reconfigurable computing and HW/SW co-design technologies to develop an efficient architecture of an automatic fingerprint authentication system (AFAS) oriented to real-time embedded applications.

Hardware-Software Co-design of a Fingerprint Matcher on Card

Nowadays, security is becoming a real need for society and a real challenge for those everyday activities such as access control, cash terminals, public transport, Internet... where user authentication is required prior to giving access to confidential information, relevant places or restricted resources. The implementation of a reliable personal recognition system not based on vulnerable topics such as physical keys or passwords is required. Biometrics-based authentication techniques (e.g. face, iris, fingerprint recognition...) in conjunction with smart cards technologies bring a challenging solution to this need. This paper describes the hardware-software co-design of a fingerprint match on card system responsible for matching two fingerprint minutiae sets in a reliable and secure way. The proposed system architecture is composed by a general-purpose 8-bit microcontroller and a 40-kgates FPGA, all embedded in a system on chip device. A good solution is detailed from a performance versus cost point-of-view

FPGA Implementation of the Ridge Line Following Fingerprint Algorithm

Most biometrics systems are implemented on high performance microprocessors executing complex algorithms on software. In order to develop a low-cost and high-speed coprocessor, floating-point computations have been substituted by fixed-point ones, and a pipeline scheme has been developed.

Biometrics-based consumer applications driven by reconfigurable hardware architectures

Nowadays the development of automatic biometrics-based personal recognition systems is a reality in the current technological age. Not only those applications demanding stringent security levels but also many daily use consumer applications request the existence of high performance computational platforms in charge of recognizing the identity of an individual based on the analysis of his/her physiological or behavioural characteristics. The state of the art points out two main open problems in the implementation of such automatic applications: on the one hand, the needed improvement of the reliability level of the existing recognition systems in terms of accuracy, security and real-time performances; on the other hand, the cost reduction of those physical platforms in charge of the processing. This work addresses those limitations of current systems and aims at finding the proper system architecture to develop this kind of high-performance applications at low cost. Because of that, those existing solutions based on expensive multiprocessor systems like HPC (High Performance Computer), GPU (Graphics Processing Unit), or PC (Personal Computer) platforms need to be discarded, and instead of them embedded system solutions based on programmable logic devices are suggested in this work. The programmability performances of FPGA (Field Programmable Gate Array) devices together with the inherent parallelism of hardware design provide the needed flexibility to develop made-to-measure coprocessors in charge of accelerating those time-critical computational tasks. To address the cost of the system, dynamically reconfigurable FPGAs are suggested in this work. The scheduling of the recognition application into a series of mutually exclusive tasks, and the reutilization of those functional resources available in the FPGA by multiplexing different coprocessors in the same area along the application execution time allows reducing the size of the device and therefore its cost at the expense of the reconfiguration overhead. The hardware-software co-design of an AFAS (automatic fingerprint-based authentication system) under two different run-time reconfigurable platforms is presented as the proof of concept of the suggested architecture. The outstanding results achieved in this work pave the way for the implementation of biometric applications by means of run-time reconfigurable FPGAs.

Design of FPGA-based Hardware Accelerators for On-line Fingerprint Matcher Systems

Nowadays fingerprints are the most widely used biometric characteristics in automatic personal authentication or identification systems. Most human recognition systems use those fingertip discontinuities called minutiae and mainly based on the ridge endings and the ridge bifurcations of the skin to perform fingerprint matching. A fingerprint pattern is thus defined by the spatial distribution of its distinctive traits. Matching two fingerprints in minutiae-based representations becomes a point pattern matching, and it consists of finding the alignment and correspondences between pairs of minutia points in both sets. Several algorithms have been proposed in the last decades to efficiently match two fingerprint minutiae sets. This paper describes the design of FPGA-based accelerators responsible for performing those computationally expensive tasks needed in the fingerprint matching process. The acceleration results obtained when partitioning the application in hardware and software tasks permits to make the conventional purely software-oriented and off-line matching algorithms suitable for on-line applications

Hardware-Software Co-design of a Fingerprint Image Enhancement Algorithm

This paper presents the implementation of a fingerprint image enhancement algorithm on a FPGA device. The design is based on a hardware-software co-design, which consists of a dedicated coprocessor that solves the parts of the algorithm with higher computational cost and an embedded microprocessor that manages the control process and executes the rest of the algorithm. In order to develop an efficient implementation, fixed-point computations have substituted the floating-point ones. The system has been implemented on a Xilinx Spartan 3 FPGA, with an external SRAM memory of 512Ktimes32 bits and using a Microblaze embedded soft-core processor. Results show that a 256times256 pixel image can be analyzed in 750 ms with a clock frequency of 50 MHz

Deployment of Run-Time Reconfigurable Hardware Coprocessors Into Compute-Intensive Embedded Applications

Day after day, embedded systems add more compute-intensive applications inside their end products: cryptography or image and video processing are some examples found in leading markets like consumer electronics and automotive. To face up these ever-increasing computational demands, the use of hardware accelerators synthesized in field-programmable gate arrays (FPGA) lets achieve processing speedups of orders of magnitude versus their counterpart CPU-based software approaches. However, the inherent increment in physical resources penalizes in cost. To address this issue, dynamically reconfigurable hardware technology definitively reached its maturity. SRAM-based reconfigurable logic goes beyond the classical conception of static hardware resources distributed in space and held invariant for the entire application life cycle; it provides a new design abstraction featured by the temporal partitioning of such resources to promote their continuous reuse, reconfiguring them on the fly to play a different role in each instant. This new computing paradigm lets balance the design of embedded applications by partitioning their functionality in space and time—through a series of mutually-exclusive processing tasks synthesized multiplexed in time on the same set of resources—and achieving thus cost savings in both area and power metrics. However, the exploitation of this system versatility requires special attention to avoid performance degradation. Such technical aspects are addressed in this work intended to be a survey on reconfigurable hardware technology and aimed at defining an open, standard and cost-effective system architecture driven by flexible coprocessors instantiated on demand on reconfigurable resources of an FPGA. This concept fits well with the functional features demanded to many embedded applications today and its feasibility has been proved with a state-of-the-art commercial SRAM-based FPGA platform. The achieved results highlight dynamic partial reconfiguration as a potential technology to lead the next computing wave in the industry.