Frank Grassert

Total leakage power optimization with improved mixed gates

Gate oxide tunneling current Igate and sub-threshold current Isub dominate the leakage of designs. The latter depends on threshold voltage Vth while Igate vary with the thickness of gate oxide layer Tox. In this paper, we propose a new method that combines approaches of dual threshold CMOS (DTCMOS), mixed-Tox CMOS, and pin-reordering. As the reduction of leakage leads to an increase of gate delay, our purpose is the reduction of total leakage at constant design performance. We modified a given technology and developed a library with a new mixed gate type. Compared to the case where all devices are set to high performance, our approach achieves an average leakage reduction of 65%, whereas design performance stays constant

Low power gate-level design with mixed-V/sub th/ (MVT) techniques

The reduction of leakage power has become an important issue for high performance designs. One way to achieve low-leakage and high performance designs is the use of multi-threshold techniques. In this paper, a new mixed-V/sub th/ (MVT) CMOS design technique is proposed, which uses different threshold voltages within a logic gate. This new technique allows the reduction of leakage power, while the performance stays constant. A set of algorithms is given assigning optimal distribution of gates. Results indicate that the new MVT approach can provide up to 40% leakage reduction by constant performance compared to dual-V/sub th/ (DVT) gate-level techniques.

Reducing leakage with mixed-V/sub th/ (MVT)

We present a new method for assignment of devices with different V/sub th/ in a double-V/sub th/-process, whereas leakage is reduced and performance increases or is constant. A mixed-V/sub th/ gate type is developed, which renders new masks unnecessary. As compared with known methods, our approach achieves an additional leakage reduction of 25% while leakage reduction in raw designs is average 65%.

DCP: a new data collection protocol for Bluetooth-based sensor networks

Two economic factors are essential for the success of wireless sensor networks as new key technology: low-cost hardware and strong prototype applications. Although not perfect, Bluetooth can be a driving technology in this domain. We present a new data collection protocol (DCP) for wireless sensor networks. DCP is tailored to Bluetooth-based sensor nodes and therefore enables sensor network applications based on inexpensive hardware. DCP is scalable, robust, and not limited to piconet or scatternet structures.

Deep Submicron Technology: Opportunity or Dead End for Dynamic Circuit Techniques

Dynamic circuit techniques offer potential advantages over static CMOS, especially if more complex logic is to be implemented. Therefore, they are extensively used in high performance designs to speed up critical subsystems. However, the speed benefit is traded off for increased power consumption, area overhead, design effort, and reduced noise margins. The continuing process of technology scaling raises further concerns of reliability and limits the wide use of dynamic logic. This paper presents evaluations in terms of area, power dissipation, and propagation delay for several dynamic logic styles as well as for static CMOS in a 90 nm technology. The intention is to assess if dynamic circuit techniques are still an option to boost performance against the background of the issues of nanotechnology. Moreover, issues of reliability and signal integrity, gained from practical experience for different testbenches, and possible solutions are discussed. Finally, an automated design flow for dynamic logic, derived from a standard CMOS flow, is presented

Dynamic single phase logic with self-timed stages for power reduction in pipeline circuit designs

True single phase clock logic techniques, e.g. with alternating arranged Nand P-logic cells, yield easily to design circuits with standard cells and high speed potential. The disadvantages are a difficult clock tree design and high power consumption. To realize every logic function, dual rail or differential styles are chosen which increase clock load. This paper presents a method to speed up dynamic single clock circuits. The advantage of asynchronous logic is that the critical path delay is the sum of only the evaluation times of the single logic blocks without wasting time for waiting, latches, or redundant logic. Therefore, this work assembles small asynchronous chains of dynamic logic blocks into one period of the global clock to minimize the unused time per clock cycle (AC-TSPC). However, the synchronous single phase clocking scheme is maintained. The advantages of this method are shorter latencies for calculations, power reduction by smaller clock trees and no need for latches, and a simpler clock distribution network due to increased clock skew tolerance. The results of the simulations of an 8/spl times/8 bit multiplier in TSPC and in AC-TSPC show an enhancement in power-reduction of 40% for the logic and of 89% for the clock tree with a latency reduction of 40% and more in comparison with TSPC.

Dynamic single-rail self-timed logic structures for power efficient synchronous pipelined designs

The realization of fast datapaths in signal processing environments requires fastest, power efficient logic styles with synchronous behavior. This paper presents a method to combine improvements on algorithm and logic level. To reduce the power consumption of dynamic logic, a method for using single-rail structures is presented including a new scheme to realize inverting logic functions. It is shown that such structure is most efficient when redundant number systems are utilized. These self-timed logic is integrated in a global clock system using the Asynchronous Chain True Single Phase Clock (AC-TSPC) logic resulting in a latch-free structure. Comparisons with other logic styles show the achievement potential. First simulations for a horizontal redundant adder slice show area and power savings of 40% and 30% compared to complementary Domino logic.

Single-rail self-timed logic circuits in synchronous designs

This paper presents a self-timed scheme for dynamic single-rail logic integrated in a single phase clock design. A generalized completion detection for generation of self-timed signals from single-rail gates is described and we show a novel application of the redundancy of a SD-adder to ease the self-timed signal generation. Further we discuss a universal evaluation scheme to overcome the problem of only non-inverting functions with dynamic single-rail gates. The presented SD-adder was integrated in a synchronous scheme and combines the advantages of simple synthesis and clock distribution for synchronous designs with fastest evaluation. Self-timed schemes result in fastest latch-free structures and robustness against clock-skew. Further the single-rail scheme on gate-level yields lower power consumption and smaller circuits. The use of inverting and non-inverting single-rail gates makes the synthesis close to standard synthesis. Simulations for the redundant adder design show area and power savings of 40% and 30% compared to complementary DOMINO logic structure.