Frank Sill

Total leakage power optimization with improved mixed gates

Gate oxide tunneling current Igate and sub-threshold current Isub dominate the leakage of designs. The latter depends on threshold voltage Vth while Igate vary with the thickness of gate oxide layer Tox. In this paper, we propose a new method that combines approaches of dual threshold CMOS (DTCMOS), mixed-Tox CMOS, and pin-reordering. As the reduction of leakage leads to an increase of gate delay, our purpose is the reduction of total leakage at constant design performance. We modified a given technology and developed a library with a new mixed gate type. Compared to the case where all devices are set to high performance, our approach achieves an average leakage reduction of 65%, whereas design performance stays constant

Low power gate-level design with mixed-V/sub th/ (MVT) techniques

The reduction of leakage power has become an important issue for high performance designs. One way to achieve low-leakage and high performance designs is the use of multi-threshold techniques. In this paper, a new mixed-V/sub th/ (MVT) CMOS design technique is proposed, which uses different threshold voltages within a logic gate. This new technique allows the reduction of leakage power, while the performance stays constant. A set of algorithms is given assigning optimal distribution of gates. Results indicate that the new MVT approach can provide up to 40% leakage reduction by constant performance compared to dual-V/sub th/ (DVT) gate-level techniques.

High-speed, low-leakage integrated circuits: An evolutionary algorithm perspective

The markets today observe users having increasing demands on processing speed and energy consumption of their mobile devices. However, processing speed as well as functionality always comes at the expense of energy and thus limits, among other things, mobility and integration density. Recent technological developments allow for the simultaneous realization of slow, low-energy consuming as well as fast, high-energy consuming gates on the very same chip. In this respect, a particular design is an abstract optimization task for which this paper applies evolutionary algorithms. These algorithms are heuristic population-based search procedures that utilize certain mechanisms known from natural evolution. In comparison to currently available deterministic optimization procedures, the evolutionary algorithms achieved some energy savings of about 10-40% on standard ISCAS test problems, while still yielding the highest processing speed possible.

Reducing leakage with mixed-V/sub th/ (MVT)

We present a new method for assignment of devices with different V/sub th/ in a double-V/sub th/-process, whereas leakage is reduced and performance increases or is constant. A mixed-V/sub th/ gate type is developed, which renders new masks unnecessary. As compared with known methods, our approach achieves an additional leakage reduction of 25% while leakage reduction in raw designs is average 65%.

Total leakage reduction by observance of parameter variations

Leakage power dissipation and parameter variations are main topics in current research. The problem of parameter variations leads to modified timing analysis. Traditionally, this is done with corner-case simulations, which are quite conservative and pessimistic approaches. This paper proposes a new statistical static timing analysis (SSTA) to improve performance predictions. Furthermore, the developed SSTA and a dual-V/sub th//dual-T/sub ox/ CMOS (DTTCMOS) design technique are combined to reduce the total leakage within designs. Compared to traditional corner-case timing analyses the proposed approach reduces leakage by an average of 70% for raw designs and by an average of 25% in pre-optimized DTTCMOS designs.

Algorithms for Leakage Reduction with Dual Threshold Design Techniques

The application of devices with different threshold voltages is a state-of-the-art VLSI design technique to reduce the power consumption based on leakage currents. As devices with reduced leakage dissipation have longer delay, the aim of such Dual Threshold CMOS (DTCMOS) approaches is the detection of non-critical gates regarding the circuits performance to exchange these with slower but less leaky gates. In our talk, we consider the optimization of DTCMOS circuits, which are modeled as directed acyclic graphs. With each vertex v of a directed acyclic graph, we associate two delay values d0(v) les d1 (v) and two leakage values c0 (v) ges c 1 (v). The objective is to choose one of the indices 0 or 1 for each vertex, such that the corresponding total delay along any directed path does not exceed the maximum circuits delay and that the total leakage is minimized. It is well-known that this problem is NP-hard. We present heuristic approaches to the problem that are based on k-cutsets and k-Sperner families in partially ordered sets

Evolving High-Speed, Energy-Efficient Integrated Circuits

State-of-the-art technologies in very large scale integration (VLSI) aim at the realization of fast energy-efficient circuits. Recent technological achievements offer a design parameter with which both the processing speed and power consumption of every single gate can be fine tuned. With respect to this design parameter, a VLSI design constitutes a multi-dimensional multi-modal optimization problem. Since existing algorithms yield only suboptimal designs, this paper investigates how genetic algorithms perform in this application domain. It turns out that genetic algorithms are able to reduce the power consumption by about 10-40%.

Biologically-Inspired optimization of circuit performance and leakage: a comparative study

State-of-the-art technologies in very large scale integration (VLSI) allow for the realization of gates with varying energy consumptions and hence delays (i.e., processing speeds) in the very same circuit. By considering this technological advent as an option, the design process can pursue two different goals: (1) making the circuit as fast as possible and (2) making non-time-critical gates slower in order minimize the circuits overall energy consumption. This paper utilizes evolutionary algorithms, a population-based heuristic optimization technique, in order to find optimal solutions. From a technological point of view, this goal can be accomplished by varying the individual threshold voltages, which determine both the devices processing speed and its leakage currents. The experimental results indicate that evolutionary algorithms yield significantly better solutions than rather traditional optimization algorithms. By maintaining populations of candidate solutions, evolutionary algorithms are able to escape from sub-optimal designs, which contrasts traditional single-point optimization approaches.